Samsung Electronics Co., Ltd.

Electronics and Telecommunications Research Institute

Hyundai Motor Company

Samsung Display Co., Ltd.

Skhynix Inc.

Kia Motors Corporation

Samsung Sds Co., Ltd.

Ajou University Industry-academic Cooperation Foundation

Industry-university Cooperation Foundation Hanyang University

Lg Electronics Inc.

Hynix Semiconductor Inc.

Hanon Systems

Doosan Infracore Co., Ltd.

Samsung Sdi Co., Inc.

Lg Innotek Co., Ltd.

Jae Hoon Kim

Myeong Wuk Jang

Ji Hoon Lee

Byoung Joon Lee

Jae Woo Park

Man Ju Oh

Jae Woong Kim

Yong-Hoon Son

Kwang-Ho Park

Joong Hong Park

Seungjae Jung

Sung Chan Choi

Do Jun Byun

Sang Hwan Park

Hyunji Song

Sung Woong Kim

Won Chan Jung

Gyeonghee Lee

Sung Won Lee

Seong Ik Hong

Byoung-Joon Lee

Byoung Sun Lee

Yool Guk Kim

Yong Sung Roh

Seung Jae Jung

Jin Ho Lee

Juhyun Kim

Younghyun Kim

Ung Hwan Pi

Joonmyoung Lee

Geun Tak Kim

Kwangseok Kim

Se Chung Oh

Keewon Kim

Byeong Chul Kim

Yoon Ho Kang

Do Seob Ahn

Myoung Seo Kim

Hee Ju Shin

Yoo La Hwang

Eui Yul Choi

Min Sik Chu

Dong Hoon Kwak

Jung Won Kang

Hyun Min Cho

Jung Ho Kim

Jong Hyun Lee

Cheol Mo Jeong

Yong-Sung Park

Kyung Hun Jang

Won Geun Ryu

Jung Hoon Kim

Sung-Won Lee

Dae Jong Kim

Jin Young Lee

Hyun Seo Kang

Young Sun Kim

Kwi Seong Jeong

Hoon Ryu

Nae-Soo Kim

Young Il Kim

Deock Gil Oh

Seong Jun Bae

Whankyun Kim

Truong Cong Thang

Young Soon Heo

Soon Heung Jung

Hyoung Jun Park

Kyungtae Nam

Geon Min Yeo

Eunsun Noh

Sang Taick Park

Mi Suk Huh

Tae Hee Kim

Young Moo Lee

Sang Hoon Park

Sung Jae Yun

Ki Ho Kim

Yeonjoo Choi

Jong Dal Lee

Sung Chul Lee

Dong Woo Shin

Yangseob Kim

Keo Sik Kim

Gain Kim

Hang Jae Lee

Young Bae Ko

Eun Kyoung Jeon

Kwang Hoon Han

Eui Cheol Lim

Sang Uk Lee

Kwon Seob Lim

Woo Sub Shim

Bo Gyeong Kang

Young Jin Noh

Yuk Hyun Nam

Cha You Lim

Byung Su Kang

Young-Bae Ko

An inkjet printing apparatus may include a stage on which a substrate is seated; a nozzle part disposed above the stage and spraying an ink onto the substrate, the ink containing a solvent and solid substances; and a head part that supplies the ink to the nozzle part. The nozzle part includes an internal flow path extended in a first direction, through which the ink is supplied from the head prat; and an inlet in which an entrance area is defined. The ink is introduced in a second direction intersecting the first direction from the internal flow path through the entrance area. The inlet includes an inclined surface adjacent to the entrance area and defining the entrance area; and a flat surface parallel to the first direction. An angle between the inclined surface and the flat surface is an acute angle.

Inkjet printing apparatus

A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

Method for forming a three-dimensional semiconductor memory device with an improved etching step

A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

Semiconductor memory device including capacitor with a dielectric film on an upper plate region, a lower plate region, and a side surface of a connecting region therebetween

A memory module may include J memory chips configured to input/output data in response to each of a plurality of translated address signals; and an address remapping circuit configured to generate a plurality of preliminary translated address signals by adding first correction values to a target address signal provided from an exterior of the memory module, and to generate the plurality of translated address signals by shifting all bits of each of the plurality of preliminary translated address signals so that K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to other positions of each bit string.

Semiconductor memory apparatus, memory module, and memory system including memory module

A plasma processing apparatus may include a lower electrode supporting a wafer; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring. The focus ring may include a lower region and an upper region disposed on the lower region, and the upper region increases in electrical conductivity as the upper region is closer to the lower region.

Plasma processing apparatus

This application relates to a coating layer composition and a coating layer formed using the coating layer composition. The coating layer composition includes a heat-resistant binder, a hydroxy group-containing polyimide particle, a silane cross-linking agent, and a solvent. The hydroxy group-containing polyimide particle and the functional group-containing silane cross-linking agent form a core-shell structured organic particle in which a core portion is derived from the hydroxy group-containing polyimide particles and a shell portion that is derived from the functional group-containing silane cross-linking agent. The shell portion is on the surface of the core portion in the core-shell structured organic particle. The application also relates to a separator for a rechargeable lithium battery and a rechargeable lithium battery including the separator having a coating layer formed using the coating layer composition.

Composition for coating layer including heat-resistant binder, hydroxy-containing polyimide particle, and silane crosslinker, separator for rechargeable lithium battery including coating layer formed therefrom and rechargeable lithium battery including the same

A display device includes a plurality of pixels, a first bank defining light emission regions of the plurality of pixels, a first electrode and a second electrode which are spaced apart from each other in each of the light emission regions, and a plurality of light emitting elements disposed between the first electrode and the second electrode. The first bank, the first electrode, and the second electrode include a same material.

Display device having a first bank defining light emission regions and method of manufacturing the same

A memory system includes: a main memory device configured to include a plurality of row lines; a cache memory device configured to include a plurality of cache lines for caching data stored in the row lines, each cache line including cache data, a row hammer state value for storing an access number of a corresponding row line, and an access selection bit set according to the row hammer state value; and a memory controller configured to control an access operation to be performed on one of the main memory device and the cache memory device, which is selected according to the access selection bit of a cache-hit cache line, in response to a request from a host.

Memory system and operating method thereof

A memory system includes a host circuit and a memory circuit. The host circuit controls a bandwidth of a command-address signal based on data driving cycle information. The memory circuit performs an input/output operation based on the command-address signal.

The present technology relates to an electronic system including a host and a memory system. The host includes a request merge manager configured to generate one or more operation request sets, a first request set queue configured to store one or more of transmission request sets and operation request sets, a first scheduler configured to control the priorities of the operation request sets and the transmission request sets, a second request set queue configured to store the operation request sets sequentially output from the first request set queue, a second scheduler configured to generate a transmission request set, and a request set detector configured to transmit, to the first scheduler, request information on a request set having a highest priority.

Electronic system having memory system and host for managing request set queue

A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

Semiconductor memory device and method for manufacturing the same

A method for clustering based on unsupervised learning according to an embodiment of the invention enables clustering for newly generated patterns and is robust against noise, and does not require tagging for training data. According to one or more embodiments, noise is accurately removed using three-dimensional stacked spatial auto-correlation, and multivariate spatial probability distribution values and polar coordinate system spatial probability distribution values are used as learning features for clustering model generation, making them robust to noise, rotation, and fine unusual shapes. In addition, clusters resulting from clustering are classified into multi-level clusters, and stochastic automatic evaluation of normal/defect clusters is possible only with measurement data without a label.

Method and apparatus for detecting defect pattern on wafer based on unsupervised learning

Provided is a hypertube transport system. Specifically, provided are a magnetically-levitated train and an infrastructure-system in which same travels, comprising: refrigerant for cooling compressed air of a hypertube train, and a compressed air cooling system utilizing the refrigerant; an apparatus and method for controlling trains operating in a vacuum tube; superconducting switches for superconducting magnets for magnetic levitation; a driving stability apparatus for the hypertube transport system; a control apparatus for trains of the hypertube transport system; and an energy harvester.

Hypertube transport system

A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

Semiconductor memory device

A variable resistance memory device including a substrate; horizontal structures spaced apart from each other in a first direction perpendicular to a top surface of the substrate; variable resistance patterns on the horizontal structures, respectively; and conductive lines on the variable resistance patterns, respectively, wherein each of the horizontal structures includes a first electrode pattern, a semiconductor pattern, and a second electrode pattern arranged along a second direction parallel to the top surface of the substrate, and each of the variable resistance patterns is between one of the second electrode patterns and a corresponding one of the conductive lines.

Variable resistance memory device

Growing community of inventors

Yongin-si, South Korea

Jae Hoon Kim