Samsung Electronics Co., Ltd.

Jae-Hoon Joo

Sang-Seok Kang

Jong-hyun Choi

Yun-Sang Lee

Byung-heon Kwak

Byung-chul Kim

Kyu-Chan Lee

Jei-Hwan Yoo

Yun-sang Lee

Jin-Seok Lee

Hyung-Dong Kim

Jong-Hyoung Lim

Jae-hyoung Park

Sung-hyup Kim

Sung-Yong Park

Sang-Man Byun

Jong-Eon Lee

Tae-Sik Son

Sang-Boo Kang

Byung-Heon Kwak

Sang-Kyu Yoo

Jeong-min Na

Kang-Young Cho

Sang-Suk Kang

Jae-Geun Kim

Young-Ok Cho

Chang-hag Oh

Na-Rae Kim

Hee-Joong Oh

Young-Min Jang

Chang-Joo Choi

An apparatus for clamping a probe card may include a body portion, an inner clamping portion and a plurality of outer clamping portions. The body portion may be arranged between a printed circuit board (PCB) of the probe card and a test head. The inner clamping portion may be integrally formed with an upper surface of the body portion. The inner clamping portion may be configured to affix a central portion of the PCB to the test head. The outer clamping portions may be integrally formed with side surfaces of the body portion. The outer clamping portions may be configured to affix a portion surrounding the central portion of the PCB to the test head. Thus, a contact area between the clamping apparatus and the PCB may be increased.

Apparatus for clamping a probe card and probe card including the same

Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

Fuse circuit and semiconductor device having the same

In a layout structure of pads and a structure of pad used for a test or wire bonding of a semiconductor device, a size of at least one or more non-wire bonding pads is relatively small as compared with a size of at least one or more pads to be used for wire bonding of the semiconductor device. In the pad structure, a pad includes a wire bonding region that has an embossed surface for a portion of top metal layer within a determined pad size to improve the bonding process, and a probe tip contact region that does not have the embossed surface for a surface portion of the top metal layer within the determined pad size, so as to reduce wear of probe tip during testing of the device. Pad pitch can thereby be increased within a limited region, and peripheral circuits can be further formed in regions that would have been occupied in a conventional pad formation region. Higher integration of semiconductor devices and reduced wear of probe tip in probing is thereby realized.

Semiconductor device including wire bonding pads and pad layout method

Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.

Dynamic random access memory and communications terminal including the same

A bit line pre-charge circuit of a semiconductor memory device includes a pre-charge circuit connected between a pair of bit lines for pre-charging the pair of bit lines in response to a pre-charge control signal and a pre-charge voltage transmitting circuit for transmitting a pre-charge voltage to the pre-charge circuit in response to the pre-charge control signal. A voltage drop in a pre-charge voltage generation line may be prevented when a short circuit is formed between a word line and a pair of bit lines, and current consumption during a standby operation of the semiconductor memory device may also be reduced, by preventing current from flowing from the pair of bit lines to the pre-charge voltage generation line.

Bit line pre-charge circuit of semiconductor memory device

A semiconductor memory device of the invention includes: main decoders for generating wordline enable signals in response to first decoding signals, a first precharge signal, and a second precharge signal; wordline drivers for wordline drive signals in response to the wordline enable signals and second decoding signals; and a circuit for generating the second precharge signal in response to a command signal. The wordline drive signals are inactivated in sequence in response to the first decoding signals and the second precharge signal, in order to reducing ground noises.

Decoding circuit for controlling activation of wordlines in a semiconductor memory device

A layout of a bit line sensing control circuit for a semiconductor memory device includes two bit line pairs extending in a first direction. A power contact is arranged between the two bit line pairs. A power gate is arranged around the power contact. A plurality of sense transistors respectively have a plurality of sense transistor gates. The plurality of sense transistor gates are arranged around the power gate. A pair of control line contacts is arranged in a second direction at an adjacent location outside the two bit line pairs. A control line extends in the second direction and is connected to the power gate through the pair of control line contacts. A power line extends in the second direction adjacent to the control line and is connected to an active area surrounded by the power gate through the power contact.

Bit line sensing control circuit for a semiconductor memory device and layout of the same

A semiconductor memory device includes first and second isolation transistors for electrically connecting/isolating a pair of bitlines to/from a sense amplifier circuit, and a MOS transistor having a source region that is shared with one of sources of the first and second isolation transistors. The MOS transistor may be used as a bitline boosting capacitor.

Arrangement of bitline boosting capacitor in semiconductor memory device

Integrated circuit memory devices include first and second memory cell arrays, first and second transmission parts between the first and second memory cell arrays, and first and second input/output selection parts between the first and second memory cell arrays, wherein the first transmission part is adjacent the first input/output selection part and wherein the second transmission part is adjacent the second input/output selection part. A transistor in the first transmission part and a transistor in the first input/output selection part can share a first common source/drain region. A transistor in the second transmission part and a transistor in the second input/output selection part also can share a second common source/drain region. First and second input/output selection parts also may be provided between the first and second transmission parts. At least one sense amplifier part may be provided between the first and second input/output selection parts.

Integrated circuit memory devices including transmission parts that are adjacent input/output selection parts

A semiconductor memory device including a plurality of memory blocks having associated with one or more circuit blocks therearound, and a plurality of input/output lines associated with the memory blocks, is disclosed. The input/output lines are divided into at least a first group and a second group. First portions of the input/output lines of the first group are arranged between the adjacent memory blocks while first portions of the input/output lines of the second group are arranged within the circuit blocks around the adjacent memory blocks. Second portions of the input/output lines of the first group are arranged on the circuits blocks around the memory blocks while second portions of the input/output lines of the second group are arranged between the adjacent memory blocks.

Input/output line structure of a semiconductor memory device

An internal power supply circuit for use in a semiconductor device includes a clamp circuit for clamping an internal voltage to a constant level. The clamped internal voltage is distributed to internal circuits of the semiconductor device through an output node. When the internal voltage rises momentarily due to noise in the internal power supply circuit due to open-circuit phenomenon, the rising internal voltage is discharged through the clamp circuit, thereby maintaining the internal voltage at a constant value. The clamp circuit includes a first transistor for discharging the output node, and a diode-connected transistor for generating a charge voltage at the gate of the first transistor. The threshold voltage of the diode-connected transistor is preferably equal to or lower than the threshold voltage of the first transistor.

Growing community of inventors

Seongnam-si, South Korea

Jae-Hoon Joo