Samsung Electronics Co., Ltd.

Jae-Hoon Jang

Won-Seok Cho

Han-Soo Kim

Sun-Il Shim

Hansoo Kim

Soon-Moon Jung

Jae-Hun Jeong

Donghyuk Chae

Jaehun Jeong

Youngho Lim

Young-Hwan Son

Sung-Min Hwang

Young-Chul Jang

Shin-Hwan Kang

Ki-Hyun Kim

Chang-Sup Lee

Dong-seog Eun

Yang-Soo Son

Kohji Kanamori

Jae-Duk Lee

Kwang-soo Kim

Jong-Hyuk Kim

Jee-Hoon Han

Min-Sung Song

Yong-Seok Kim

Joon-Hee Lee

Sung-jin Kim

Jinman Han

Tae-hun Kim

Jae-Joo Shim

Hoo-Sung Cho

Young-Jin Jung

Kun-Ho Kwak

Min-kyung Bae

Sung-Yun Lee

Sunil Shim

Sang-Yong Park

Byoungkeun Son

Hoon Lim

Byeong-In Choe

Jun-Beom Park

Jin-Man Han

Hui-Chang Moon

Young-Seop Rah

Jong-In Yun

Heon-kyu Lee

In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.

Integrated circuit device including vertical memory device and method of manufacturing the same

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Nonvolatile memory devices, operating methods thereof and memory systems including the same

Non-volatile memory devices, operating methods thereof and memory systems including the same

A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

Vertical type semiconductor devices and methods of manufacturing the same

Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

Vertical non-volatile memory device, method of fabricating the same device, and electric-electronic system having the same device

A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

Vertical non-volatile memory device with high aspect ratio

A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, a common source extension structure including a first semiconductor layer having an n-type conductivity and a gate insulating layer between the substrate and the channel structures, a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity. An upper portion of the common source extension structure has a first width, and a lower portion of the common source extension structure has a second width smaller than the first width.

Semiconductor device including vertical channel layer

A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

Vertical non-volatile memory device having channel-accomodating opening formed of etch stop region in lower stack layers

Growing community of inventors

Seongnam-si, South Korea

Jae-Hoon Jang