Samsung Electronics Co., Ltd.

Jae-Hong Min

Dong-Uk Kim

Chan-Kyung Kim

Young-Nam Hwang

Jin-Min Kim

Sang-Kil Lee

Soon-Young Kim

Han-Joon Kim

Provided is a memory device that includes a memory bank including a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines of the memory device intersect each other, a sense amplifier configured to amplify a signal transmitted through selected bit lines among the plurality of bit lines, and an arithmetic circuit configured to receive a first operand from the sense amplifier, receive a second operand from outside the memory device, and perform an arithmetic operation by using the first operand and the second operand, based on an internal arithmetic control signal generated in the memory device.

Memory device including arithmetic circuit and neural network system including the same

A method and system for maximizing bandwidth of a Peripheral Component Interconnect Express (PCIe) Peer-to-Peer (P2P) connection determine a maximum bandwidth and a maximum read request size of a first device, determining a maximum bandwidth and a minimum payload size of a second device, calculate a calculated maximum payload size of the second device by using the maximum read request size of the first device and a bandwidth ratio between the first device and the second device, compare the minimum payload size of the second device with the calculated maximum payload size, and set an operational payload size of the second device to the calculated maximum payload size when the calculated maximum payload size is equal to or greater than the minimum payload size.

System and method for maximizing bandwidth of PCI express peer-to-peer (P2P) connection

Growing community of inventors

Yongin-si, South Korea

Jae-Hong Min