Hynix Semiconductor Inc.

Skhynix Inc.

Sejong University

Lg Display Co., Ltd.

Samsung Electronics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Markany Inc.

Jae Hong Kim

Seung Jin Yeom

Deok-kee Kim

Joon Seok Oh

Seo Woo Nam

Kwon Hong

Dong Ha Jung

Baek Mann Kim

Nam Yeal Lee

Jae Hyoung Koo

Jeong Tae Kim

Kyong Ho Lim

Eun Shil Park

Honggyun Kim

Eun-Shil Park

Hyoung Jun Kim

Jong Uk Choi

Won Kyu Han

Dong Gyou Lee

Jang Hoon Lee

Dae Soo Park

Don Gyou Lee

Kyu Sun Cho

Sung Goon Kang

Various embodiments of the present invention relate to a method for accurately detecting, by an electronic device, that a tray for loading a SIM card is detached. An electronic device according to various embodiments of the present invention may comprise: a tray for loading a SIM card; a first processor electrically connected to the tray; and a second processor electrically connected to the first processor, wherein the first processor is configured to transfer a pre-event to the second processor when a detachment event for the tray is detected, and the second processor is configured to identify, in each designated period, whether the SIM card is erroneous; and delay identification of whether the SIM card is erroneous, in response to reception of the pre-event. The present invention may further include various other embodiments.

Electronic device in which tray for loading SIM card is inserted, and control method therefor

An e-fuse for a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other; a semiconductor layer formed under the gate metal, and forming a capacitor together with the gate metal; and a first oxide layer formed under the gate metal and on both sides of the semiconductor layer.

E-fuse for use in semiconductor device

An e-fuse for use in a semiconductor device includes first and second electrodes; a gate metal coupling the first and second electrodes with each other; a first oxide layer formed under the gate metal; and a gate oxide layer formed between a bottom end of the gate metal and a top end of the first oxide layer.

A fuse of a semiconductor device may include: a fuse link suitable for extending in a first direction and connecting first and second electrodes; a dummy strip suitable for extending in the first direction, and with a predetermined distance from the fuse link in a second direction perpendicular to the first direction; and an air channel formed between the fuse link and the dummy strip to contact with the fuse link.

Fuse of semiconductor device and method for forming the same

An anti-fuse for a semiconductor device includes an electrode; a gate metal formed to extend from the electrode; a gate oxide layer formed under the gate metal; a semiconductor layer formed under the gate oxide layer to overlap with a center portion of the gate metal; and a first oxide layer formed under the gate metal and the gate oxide layer and on both sides of the semiconductor layer.

Anti-fuse for use in semiconductor device

Provided are a method and apparatus for automatically splitting an object and a method, apparatus, and system for registering a file. The method for splitting an object includes receiving the data of a stereolithography (STL) file representing a 3D image, tagging vertex coordinates corresponding to objects included in the 3D image so that the vertex coordinates are classified for each object, and splitting each of the objects included in the 3D image based on the tagged vertex coordinates.

Method and apparatus for automatically splitting object and method, apparatus, and system for registering file

An optical measuring apparatus for measuring optical characteristics of a stereoscopic display device includes a test image supplier for generating a 3D test signal, a 3D display for displaying left-eye image and/or right-eye image based on the 3D test signal supplied from the test image supplier, a image selection member for selectively transmitting the left-eye image and right-eye image to be displayed on the 3D display, and a light measuring device for measuring intensity or color information of the image transmitted via the image selection member.

Optical measuring apparatus and method of stereoscopic display device

An optical measuring apparatus and method for a stereoscopic display device are capable of measuring optical characteristics of the stereoscopic display device. The optical measuring apparatus includes a test image supplier for generating a 3D test signal, a 3D display for displaying left-eye image and/or right-eye image based on the 3D test signal supplied from the test image supplier, an image selection member for selectively transmitting the left-eye image and right-eye image to be displayed on the 3D display, and a light measuring device that measures luminance of the image transmitted via the image selection member and calculates 3D image crosstalk of the left eye image and the right eye image based on the measured luminance.

An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an MoOlayer and an Mo layer. The metal line is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Electrical conductor line having a multilayer diffusion barrier for use in a semiconductor device and method for forming the same

A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer on the monolayer with the catalytic particles. The method includes the steps of forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the metal line forming region; adsorbing catalytic particles on the self-assembled monolayer; forming using an electroless process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper layer on the copper seed layer to fill in the metal line forming region.

Method for forming copper line having self-assembled monolayer for ULSI semiconductor devices

A metal line having a MoSi/Mo diffusion barrier of a semiconductor device and corresponding methods of fabricating the same are presented. The metal line includes an insulation layer, a diffusion barrier, and a metal layer. The insulation layer is formed on a semiconductor substrate and has a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a stack structure composed of a MoSilayer and a Mo layer. The metal layer is formed on the diffusion barrier which fills in the metal line forming region of the insulation layer.

[object Object]

A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer has a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier includes a stack structure including an MoSiNlayer and an Mo layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Metal line of semiconductor device having a diffusion barrier and method for forming the same

The present invention discloses to a method of forming a gate electrode, the method according to the present invention comprises the steps of forming a lower amorphous silicon layer using silane (SiH) gas and nitrous oxide (NO) gas; forming an upper amorphous silicon layer on the lower amorphous silicon layer; and crystallizing the lower and upper amorphous silicon layers through a thermal process.

Method of forming gate electrode

A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and a metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer, and the diffusion layer has a multi-layered structure of an Ru layer, an RuOlayer, an IrOlayer, and a Ti layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Metal line of semiconductor device and method for forming the same

A method of fabricating a flash memory device is disclosed. The method comprises forming a first insulating layer on a semiconductor substrate; accumulating nitrogen at an interface between the semiconductor substrate and the first insulating layer to form a second insulating layer at the interface; and implanting oxygen into the second insulating layer to convert the second insulating layer to a third insulating layer.

Growing community of inventors

Gyeonggi-do, South Korea

Jae Hong Kim