Samsung Electronics Co., Ltd.

Korea Food Research Institute

Jae-Ho Park

Tae-Hee Lee

Sanghoon Baek

Taejoong Song

Sang-Kyu Oh

Tae-Joong Song

Sang-Hoon Baek

Won-sik Kang

Seung Young Lee

Seolun Yang

Myung Gil Kang

Giyoung Yang

Hyeon Gyu You

Ji Su Yu

Hyosig Won

Min Jung Kim

Jintae Kim

Jong-Hoon Jung

Seung-Young Lee

Jin-tae Kim

Dal-Hee Lee

Hyo-Sig Won

Gi-young Yang

Ji-Su Yu

Jae-Boong Lee

Jin-Young Lim

Hyoung-Rae Kim

Hye Young Kim

Hyeon-gyu You

Kang-Hyun Baek

Yi Seul Kim

Seung Man Lim

Tea-Seog Um

Hee Jin Son

Mee Ra Rhyu

In-Sik Kim

Kwang-Ok Jeong

Suk-Lae Kim

Yoon-Oh Han

Sung-Bo Oh

Hyoung-Woo Jeon

Na-Rae Yun

Young-Taek Yoo

An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

Integrated circuits including integrated standard cell structure

An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

Integrated circuit including integrated standard cell structure

A semiconductor device is provided. The semiconductor device includes a first cell region and a filler region that are adjacent each other in a first direction. The semiconductor device includes an active pattern extending in the first direction, inside the first cell region, a gate electrode extending in a second direction intersecting the first direction, on the active pattern, a gate contact electrically connected to an upper surface of the gate electrode, a source/drain contact electrically connected to a source/drain region of the active pattern, adjacent a side of the gate electrode, a connection wiring that extends in the first direction over the first cell region and the filler region, and is electrically connected to one of the gate contact or the source/drain contact, and a filler wiring that is inside the filler region. A related layout design method and fabricating method are also provided.

Semiconductor devices, layout design methods for the same, and methods for fabricating the same

A semiconductor device includes first group active fins and a first diffusion prevention pattern. The first group active fins are spaced apart from each other in a second direction, and each of the first group active fins extends in a first direction different from the second direction on a first region of a substrate including the first region and a second region. The first diffusion prevention pattern extends on the first region of the substrate in the second direction through the first group active fins. The first group active fins include first and second active fins. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end of the second active fin in the first direction.

Semiconductor devices

Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.

Integrated circuit including multiple-height cell and method of manufacturing the integrated circuit

A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Semiconductor device and method of fabricating the same

A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.

Standard cell library and methods of using the same

A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns.

Integrated circuit layout design system and method

A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base.

Semiconductor device with active fins separated by shallow and deep trench isolations and method for fabricating the same

A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region and extending in a first direction parallel to a top surface of the substrate, a first source/drain region and a second source/drain region disposed in the active region at both sides of the gate structure, respectively, and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively. The distance between the gate structure and the first modified contact is smaller than the distance between the gate structure and the second modified contact.

Semiconductor device and method for manufacturing the same

A coniferyl alcohol or a Compositae family, Brassicaceae family, Umbelliferae family, Lamiaceae family, Liliaceae family or Amaranthaceae plant extract provides various uses associated with hTRPA1 activation, and, being a natural compound, involves relatively few side effects in the body and has substantial industrial applicability. The coniferyl alcohol or the Compositae family, Brassicaceae family, Umbelliferae family, Lamiaceae family, Liliaceae family or Amaranthaceae plant extract of the present invention not only will be a novel medical or food raw material which is helpful in maintaining homeostasis in the body associated with hTRPA1 activation, but can also be used to advantage in hTRPA1 antagonist screening.

hTRPA1-activating composition and use thereof

A voltage generator includes a boosting circuit boosting a power voltage to generate first through fourth voltages, and a boosting controller controlling the boosting circuit. The boosting controller sets the third and fourth voltages to a voltage level lower than that of a ground voltage while the first and second voltages are generated, so that a plurality of voltages may be stably generated, i.e., without latch-up.

Methods and apparatus for latch-up free boosting

Growing community of inventors

Suwon-si, South Korea

Jae-Ho Park