Samsung Electronics Co., Ltd.

Jae Ho Jeong

Jung Hwan Lee

Sun Young Lee

Woo Sung Yang

Lee Eun Ku

In Su Noh

Sun Young Kim

Jang Gn Yun

Hyun Sook Yoon

A semiconductor device includes a structure including gate electrodes and interlayer insulating layers alternately stacked on an upper surface of a substrate, trenches passing through the structure; and a groove passing through a portion of the structure. The gate electrodes include word lines, and first and second select lines. The word lines are stacked in a vertical direction upwardly from the upper surface of the substrate. The first and second select lines are on the word lines, and are spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate. The trenches include a first trench and a second trench spaced apart from the first trench. The groove is on the word lines. The groove and a portion of the first trench are between the first select line and the second select line. The second trench is spaced apart from the select lines.

Semiconductor devices including flared source structures

A semiconductor device can include a semiconductor substrate having a memory cell region and a pad region that is adjacent to the memory cell region, the pad region can include a first pad region, a second pad region between the memory cell region and the first pad region, and a buffer region that is between the first and second pad regions. A separation source structure can include a first portion and a second portion that are parallel to each other in a plan view of the semiconductor device. A first source structure and a second source structure can be disposed between the first and second portions of the separation source structure, where the first and second source structures can have end portions that oppose each other, the first source structure being disposed in the first pad region, and the second source structure being disposed in the second pad region. A gate group can be disposed in the memory cell region and the pad region between the first and second portions of the separation source structure, where each of the end portions of the first and second source structures has a planar shape, and a width of each end portion increases and then decreases as each of the end portions extends toward the other.

A memory device includes a cell region including a channel region extending to be perpendicular to an upper surface of a substrate, a plurality of gate electrode layers stacked on the substrate adjacently to the channel region, a peripheral circuit region including a first active region disposed in the vicinity of the cell region, a second active region having an area larger than an area of the first active region, a plurality of first contacts connected to the first active region, and a plurality of second contacts connected to the second active region. A distance between the plurality of first contacts is less than that between the plurality of second contacts.

3-dimensional memory device having peripheral circuit devices having source/drain contacts with different spacings

Growing community of inventors

Suwon-si, South Korea

Jae Ho Jeong