Samsung Electronics Co., Ltd.

Jae-ho Choi

Sung-Il Cho

Jun-Young Ko

Se-Jin Yoo

Chan-Sik Kwon

Seok-Won Jeong

Jin-wook Jang

A semiconductor package includes a wiring substrate including a plurality of solder pads; a chip including a plurality of chip pads connected to the solder pads through a plurality of solders; a sealing layer configured to seal the chip and the solders, at least one void being between the solders; and a solder extrusion prevention layer on one sidewall of the solder exposed by the at least one void.

Semiconductor package and method of manufacturing the same

A test apparatus for a semiconductor package comprising an X-ray analyzer acquiring an X-ray image of the semiconductor package and detecting a thickness of the semiconductor package from the X-ray image, and a thermal reaction analyzer applying a voltage to the semiconductor package and detecting a failure position of the semiconductor package using a surface temperature of the semiconductor package and the thickness of the semiconductor package may be provided.

Test apparatus for semiconductor package

Growing community of inventors

Cheonan-si, South Korea

Jae-ho Choi