Samsung Electronics Co., Ltd.

Jae-ho Ahn

Jong-Min Lee

Jang-Gn Yun

Joon Sung Lim

Ho-Jun Seong

There is provided a semiconductor device having an arrangement structure in which high-density line patterns having relatively small widths and relatively tight pitches may be formed. The semiconductor device includes a plurality of line patterns that are spaced apart from one another. The plurality of line patterns include a plurality of main lines that have a first gap therebetween and extend in a first direction and a plurality of sublines that are bent from one end of each of the plurality of main lines. The plurality of sublines have therebetween a distance that is greater than the first gap, and may be spaced apart from extension lines that extend from the one end of each of the plurality of main lines corresponding to the plurality of sublines in the first direction.

Semiconductor devices

A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location. To form the plurality of line patterns including the at least two continuous line repetition units, a plurality of reference patterns are formed repeatedly at a uniform reference pitch on a feature layer. A plurality of first spacers covering both side walls of each of the plurality of reference patterns are formed. A plurality of second spacers covering both side walls of each of the plurality of first spacers are formed by removing the plurality of reference patterns. The feature layer is etched using the plurality of second spacers as an etch mask by removing the plurality of first spacers.

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Seoul, South Korea

Jae-ho Ahn