Electronics and Telecommunications Research Institute

Jae Heon Shin

Seong Jae Lee

Moon Gyu Jang

Yark Yeon Kim

O Kyun Kwon

Won Seok Han

Young Gu Ju

Kyung Hyun Kim

Sang Hee Park

Hyun Woo Song

Jong Hee Kim

Woo Seok Cheong

Byueng Su Yoo

Chul Huh

Hye Yong Chu

Chi Sun Hwang

Gun Yong Sung

Min Ki Ryu

Tae Youb Kim

Nae Man Park

Rae Man Park

Kwan Sik Cho

Jung Rae Ro

Jong Heob Baek

Provided herein is an electrostatic capacitive type window integrated touch screen panel and a method for manufacturing a touch screen panel thereof, the method comprising: forming an oxide metal oxide (OMO) hybrid electrode on a strengthened substrate; and etching the OMO hybrid electrode and forming a pattern, and forming a pattern insertion layer on the pattern, wherein the OMO hybrid electrode is formed by depositing a bottom-layer, metal-layer and top-layer on top of the strengthened substrate, and the pattern insertion layer is formed based on an oxide having a refractive index of a certain range.

Method for manufacturing touch screen panel and touch screen panel

Provided are a method and apparatus for modeling source-drain current of a TFT. The method includes receiving sample data, the sample data including a sample input value and a sample output value; adjusting modeling variables according to the sample data; calculating a current model value according to the adjusted modeling variables; when a difference between the calculated current model value and the sample output value is smaller than a predetermined threshold value, fitting a current model by applying the adjusted modeling variables to the current model; applying actual input data to the fitted current model; and outputting a result value corresponding to the actual input data, wherein the current model is a model for predicting the source-drain current of the TFT.

Method and apparatus for modeling source-drain current of thin film transistor

Due to the indirect transition characteristic of silicon semiconductors, the light extraction efficiency of a silicon-based light emitting diode is lower than that of a compound semiconductor-based light emitting diode. For this reason, there are difficulties in practically using and commercializing silicon-based light emitting diodes developed so far. Provided is a silicon-based light emitting including: a substrate with a lower electrode layer on a lower surface thereof; a lower doped layer that is formed on an upper surface of the substrate and supplies carriers to an emitting layer; the emitting layer that is a silicon semiconductor layer including silicon quantum dots or nanodots formed on the lower doped layer and has a light-emitting characteristic; an upper doped layer that is formed on the emitting layer and supplies carriers to the emitting layer; an upper electrode layer formed on the upper doped layer; and a surface structure including a surface pattern formed on the upper electrode layer, a surface structure including an upper electrode pattern and an upper doped pattern formed by patterning the upper electrode layer and the upper doped layer, or a surface structure including the surface pattern, the upper electrode pattern, and upper doped pattern, wherein the surface structure enhances the light extraction efficiency of light emitted from the emitting layer according to geometric optics.

Silicon-based light emitting diode for enhancing light extraction efficiency and method of fabricating the same

Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).

Schottky barrier tunnel single electron transistor and method of manufacturing the same

An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.

Process of manufacturing an N-type Schottky barrier tunnel transistor

Provided is a semiconductor optical device having a current-confined structure. The device includes a first semiconductor layer of a first conductivity type which is formed on a semiconductor substrate and includes one or more material layers, a second semiconductor layer which is formed on the first semiconductor layer and includes one or more material layers, and a third semiconductor layer of a second conductivity type which is formed on the second semiconductor layer and includes one or more material layers. One or more layers among the first semiconductor layer, the second semiconductor, and the third semiconductor layer have a mesa structure. A lateral portion of at least one of the material layers constituting the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer is recessed, and the recess is partially or wholly filled with an oxide layer, a nitride layer or a combination of them. The semiconductor optical device having the current-confined region is mechanically reliable, highly thermally conductive, and commercially preferable and can be used in a wavelength range for optical communications.

Semiconductor optical device having current-confined structure

A device using an ambipolar transport of an SB-MOSFET and a method for operating the same are provided. The SB-MOSFET includes: a silicon channel region; a source and a drain contacted on both sides of the channel region and formed of material including metal layer; and a gate formed on the channel region, with a gate dielectric layer interposed therebetween. Positive (+), 0 or negative (&#x2212;) gate voltage is selectively applied to the gate, the channel becomes off-state when the gate voltage between a negative threshold voltage and a positive threshold voltage is applied, and the channel becomes a first on-state and a second on-state when the gate voltage is lower than the negative threshold voltage or higher than the positive threshold voltage. Accordingly, it is possible to implement three current states, that is, hole current, electron current, and no current. The SB-MOSFET can be applied to a multi-bit memory and/or multi-bit logic device.

Device using ambipolar transport in SB-MOSFET and method for operating the same

The present invention relates to a method of fabricating vertical-cavity surface emitting lasers being watched as a light source for long wavelength communication. The present invention includes forming a layer having a high resistance near the surface by implanting heavy ions such as silicon (Si), so that the minimum current injection diameter is made very smaller unlike implantation of a proton. Further, the present invention includes regrowing crystal so that current can flow the epi surface in parallel to significantly reduce the resistance up to the current injection part formed by silicon (Si) ions. Therefore, the present invention can not only effectively reduce the current injection diameter but also significantly reduce the resistance of a device to reduce generation of a heat. Further, the present invention can further improve dispersion of a heat using InP upon regrowth and thus improve the entire performance of the device.

Method of fabricating long wavelength vertical-cavity surface-emitting lasers

A method for fabricating a multi-channel array optical device having uniform spacing between different wavelengths and for having precise wavelengths by accomplishing wavelength adjustment and by the forming of mirror layers simultaneously through a multi-layer binary mask and a selective oxidization process. This method is especially useful for fabricating multi-channel array optical devices including multi-channel passive filters and multi-channel surface emitting laser arrays. The method includes forming a plurality of semiconductor mirror layers on a semiconductor substrate; forming an oxidization protective layer on the plurality of semiconductor mirror layers; selectively removing the oxidization protective layer by using a binary mask to expose the semiconductor mirror layer which will adjust a wavelength; oxidizing the exposed semiconductor mirror layer.

Growing community of inventors

Daejeon, South Korea

Jae Heon Shin