Skhynix Inc.

Jae-Heon Kim

Min-Suk Lee

Chan-Sik Park

Choi-Dong Kim

Jae-Hong Kim

Ki-Seon Park

Won-Joon Choi

Guk-Cheon Kim

Yang-Kon Kim

Jong-Koo Lim

Cha-Deok Dong

Bo-Mi Lee

Seung-Mo Noh

Jeong-Myeong Kim

Sung-Koo Lee

Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Electronic device and method for fabricating the same

Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.

A process information extractor circuit includes: a transistor array including a plurality of transistors, and configured such that, among the plurality of transistors, the number of transistors electrically coupled in series is adjusted depending on a code; a current source suitable for adjusting the amount of current flowing through the transistor array to a predetermined value; a comparator suitable for comparing a gate voltage of the transistors electrically coupled in series in the transistor array, with a reference voltage; and a code generator suitable for generating the code according to a comparison result of the comparator.

Process information extractor circuit

A semiconductor device may include: a pre-driving unit suitable for transmitting input data to a first node in response to a first control signal; a main driving unit suitable for outputting the input data transmitted to the first node, using a first voltage as a driving voltage; and a bias control unit suitable for supplying a second voltage to the first node in response to a second control signal, the second voltage having a different level from the first voltage.

Semiconductor device

A transmitter includes: a main pull-up driver suitable for pull-up driving an output node; and an auxiliary pull-up driver suitable for pull-up driving the output node based on a voltage of the output node, wherein the auxiliary pull-up driver compensates for non-linear driving current characteristics of the main pull-up driver.

Transmitter

Devices and method based on disclosed technology include, among others, a method for capable of providing asymmetrical arrangement of hole patterns while improving non-uniformity of an electronic device. Specifically, a method for fabricating hole patterns in one implementation includes forming a mask pattern which is defined with hole patterns of an asymmetrical arrangement with different longitudinal and transverse intervals, over a layer to be etched; and etching the layer to be etched, using the mask pattern as an etch barrier.

Growing community of inventors

Icheon-si, South Korea

Jae-Heon Kim