Samsung Electronics Co., Ltd.

Jae-gu Roh

Soo-In Cho

Moon-Gone Kim

A semiconductor memory device having a delay locked loop includes a delay locked loop and a voltage supply unit. The delay locked loop reduces the skew between a clock and data. The voltage supply unit supplies the voltages required by the delay locked loop when the delay locked loop is operating and is deactivated when the delay locked loop is not operating.

Semiconductor memory device having delay locked loop (DLL)

An integrated circuit memory device includes a pair of bit lines, a memory cell array connected to the pair of bit lines, a pair of sensing bit lines and a switching unit that connects the pair of bit lines and the pair of sensing bit lines in response to an isolation control signal transmitted through an isolation control line. An equalizer equalizes the pair of bit lines in response to an equalization signal that is transmitted through an equalization control line. A sense amplifier senses and amplifies a voltage difference between the pair of sensing bit lines. A discharge circuit is connected between the isolation control line and a reference voltage such as ground, to discharge the isolation control line into the reference voltage in response to an inverted isolation control signal that is transmitted through a complementary line of the isolation control line. Preferably, the discharge circuit comprises a field effect transistor such as an NMOS transistor, the source and drain of which are connected between the isolation control line and the reference voltage and the gate of which is connected to the complementary line of the isolation control line.

Integrated circuit memory devices including circuits and methods for

Integrated circuit memory devices having time compensated column selection capability include a column selection signal controller which performs the functions of generating: a control signal during read and write modes of operation, a read column selection enable signal based on the control signal during the read mode of operation and a write column selection enable signal based on a delayed version of the control signal during the write mode of operation, in response to a clock signal. Using this controller, the delay between generation of the control signal and the write column selection enable signal is greater than the delay between generation of the control signal and the read column selection enable signal. This greater delay provides a greater data access time (e.g., setup time) during write operations and thereby improves the reliability of these write operations by enabling data lines to become sufficiently charged and enabling sufficient time for data transfer between input/output lines and bit lines of a memory cell array, such as a DRAM array. A column selection circuit is also provided and this decoder is responsive to a column address and the read and write column selection enable signals. The memory cell array is electrically coupled by a sense amplifier to the column decoder.

Integrated circuit memory devices having time compensated column

A method of arranging a memory cell array in a semiconductor memory device, comprising the steps of dividing the memory cell array into a plurality of memory cell array areas having equal size, providing within the memory cell array a plurality of sub-normal memory cell arrays and at least one redundant memory cell array, arranging the plurality of sub-normal memory cell arrays and the at least one redundant memory cell array into the plurality of memory cell array areas, and arranging a plurality of sub-normal word line drivers, such that each sub-normal word line driver is adjacent to one of the plurality of memory cell array areas.

Method for arranging a memory cell array in semiconductor memory device

A burn-in test circuit of a semiconductor memory device with a first test circuit having output terminals connected to input terminals of a first half of plurality of word line drivers. A second test circuit has output terminals connected to input terminals of a second half of the plurality of word line drivers. The first and second tests circuits are sequentially activated to perform a burn-in test for all the memory cells.

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Suwon, South Korea

Jae-gu Roh