Lg Semicon Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Jae-Goo Lee

Young-Hyun Jun

Tae-Hyoung Kim

Chang-Man Khang

Ha-Soo Kim

A data input/output circuit for a semiconductor memory device includes a memory cell array, a latch-type sense amplifier for amplifying the cell data transmitted from the memory cell array in a read mode, a switching transistor for controlling a transmission of the cell data, and is connected between the memory cell array and the latch-type sense amplifier; and a write driver for storing an externally inputted cell data into the memory cell array in a write mode. The switching transistor separates the data line loading from the latch-type sense amplifier at a operation point of the latch-type sense amplifier, so that the operation speed of the sense amplifier is enhanced.

Data input/output circuit for semiconductor memory device

The present invention relates to a charge pump circuit which can vary an oscillation frequency for charge pumping in proportion to a charge consumption amount. The charge pump circuit includes: a voltage divider dividing a boosting voltage to a predetermined level; a voltage level sensing unit sensing a voltage difference between a divided voltage outputted from the voltage divider and a reference voltage, and outputting a control voltage corresponding to the sensed voltage difference; an oscillator circuit varying an oscillation frequency in accordance with the control voltage outputted from the voltage level sensing unit; and a charge pump performing a pumping operation in accordance with the output from the oscillator circuit, and outputting a boosting voltage.

Charge pump circuit having variable oscillation period

A negative delay circuit (NDC) has an NDC array operated in a high frequency. The circuit varies a number of unit delay stages at an input stage of the NDC array according to a locking fail signal in a low frequency region. The NDC can carry out a negative delay operation in a wide band even when a number of the stages in the NDC array is small. The present invention decreases a size of a chip, and in addition, reduces an unnecessary current consumption by preventing a locking from re-occurring at a stage in a back portion because the NDC array has a delay value less than one clock.

Negative delay circuit operable in wide band frequency

The semiconductor memory according to the present invention employs a plurality of sense amplifier drivers which individually control the sense amplifiers, or control groups of sense amplifiers, in the semiconductor memory. More specifically, the sense amplifier drivers control whether associated sense amplifiers are connected to sense amplifier array input/output lines. In this manner fewer sense amplifiers are connected to the sense amplifier array input/output lines, reducing overall current consumption.

Semiconductor memory device with improved sense amplifier driver

A bit line sense amplifier overdriving method includes a step for reaching a bit line data signal to a full swing level by driving the sense amplifiers in accordance with an overdriving voltage in an overdriving pulse interval, when an overdriving pulse signal is generated at points in which the sense amplifiers are enabled and disabled in a data read operation and a data write operation. The method maintains a sufficiently long refresh interval during a refresh operation.

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Kwangmyung, South Korea

Jae-Goo Lee