Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Globalfoundries Inc.

Jae Gon Lee

Elgin Kiok Quek

Chung Foong Tan

Eng Huat Toh

Chunshan Yin

Lee Wee Teo

Shyue Seng Tan

Sanford Chu

Shiang Yang Ong

Dong Kyun Sohn

Elgin Kiok Boone Quek

Kian Ming Tan

Purakh Raj Verma

Vincent Leong

Guangyu Huang

Jinping Liu

Henry K Utomo

Liang Choo Hsia

Victor Chan

Yung Fu Chong

Guowei Zhang

Wei Lu

Yu Jau Chen

Young Way Teh

Zhao Lun

Chew Hoe Ang

Liang-Choo Hsia

Yun Ling Tan

Shailendra Mishra

Meisheng Zhou

Lakshmi Kanta Bera

Bangun Indajang

Jun Jung Kim

Jong Ho Yang

Luona Goh

Vincent Ho

Wenzhi Gao

Hwa Weng Koh

Palanivel Balasubramaniam

Lydia Wong

Bin Yang

Ben Ong

Zhengquan Zhang

K H Alex See

Jingze Tian

An LDMOS is formed with a second gate stack over ndrift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include a device including a substrate; a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well; a source in the first well and a drain in the second well; a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well; a first gate stack on a portion of the first well; a second gate stack on a portion of the second well, the first and second gate stacks having a common gate electrode.

LDMOS with improved breakdown voltage and with non-uniformed gate dielectric and gate electrode

A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.

FinFET

A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.

Method to tune narrow width effect with raised S/D structure

An LDMOS is formed with a field plate over the ndrift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

LDMOS with improved breakdown voltage

A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility.

FinFET with stressors

An LDMOS is formed with a second gate stack over the ndrift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.

LDMOS with two gate stacks having different work functions for improved breakdown voltage

A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.

Stress liner for stress engineering

A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

Semiconductor device with reduced contact resistance and method of manufacturing thereof

An integrated circuit system that includes: providing a substrate including a first region and a second region; forming a first device over the first region and a resistance device over the second region; forming a first dielectric layer and a second dielectric layer over the substrate; removing a portion of the second dielectric layer; and annealing the integrated circuit system to remove dopant from the resistance device.

Integrated circuit system employing resistance altering techniques

A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.

Channel surface technique for fabrication of FinFET devices

Finfet

A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.

Non-volatile memory using pyramidal nanocrystals as electron storage elements

A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices.

Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof

Growing community of inventors

Singapore, Singapore

Jae Gon Lee