Hyundai Electronics Industries Co. Ltd.

Jae Goan Jeong

Gun Woo Park

Tae Woo Kim

Youn J Kim

Jae C Om

Chang Hyuk Lee

Young Seok Kim

A transistor and a method for fabricating the same that involves a forming a device isolation oxide film semiconductor substrate, forming an opening in the device isolation oxide to open the substrate and define an active region, the junction between the oxide and the substrate having a rounded profile, and then forming a complex gate electrode structure in the active region. The preferred gate electrode structure comprises a gate oxide and a stacked conductor structure having a first and a second conductor, an optional hard mask layer formed on the second conductor, an oxide layer formed on the first conductor, and nitride spacers formed on the oxide layer on the sidewalls of the gate electrode. On either side of the gate electrode structure lightly doped drain (LDD) regions and source drain regions are then formed in the active region of the semiconductor substrate. The wafer is then planarized with one or more insulating films to condition the wafer for subsequent processing.

Transistor and method for fabricating the same

The present invention discloses a method for forming a device trench isolation film for a semiconductor device having impurity regions at the sidewalls of the trench. The impurity regions increase the threshold voltage of the transistor and suppress an inverse narrow width effects. In addition, the method prevents or suppresses the phenomenon wherein an impurity in a channel region moves to the trench and lowers the threshold voltage of the transistor, decreases the leakage current, and overcomes a hump phenomenon by turning on a parasitic transistor at the sidewalls with the transistor in the active region. As a result, the electrical properties and reliability of the resulting semiconductor device are improved.

Method for forming device isolation film for semiconductor device

A semiconductor device with an electrostatic discharge (ESD) protective circuit is disclosed. In this semiconductor device with an ESD protective circuit, an n-well guard ring is formed around an NMOS field transistor of a data input buffer or around an NMOS transistor of a data output buffer. The n-well guard ring is strapped to an n-well of a PMOS field transistor and to an n-well of a PMOS transistor, and thus a PNPN path is formed toward the PMOS transistor at a positive mode of the ground voltage. Therefore, the electrical resistance between the wells of the NMOS transistors and the PMOS transistors can be reduced, thereby improving the characteristics of the ESD protective circuit and a latch-up device. Further the layout area is reduced, and thus, the characteristics and the reliability of the semiconductor device are improved.

Semiconductor device with ESD protective circuit

A thin film transistor for an antistatic circuit includes: wells formed on a silicon substrate; insulating layers for electrical isolation between electrodes formed within the wells; low density impurity diffused regions respectively interposed between the insulating layers; a first high-density impurity diffused region formed within one low-density impurity diffused region; a second high-density impurity diffused region formed within the other low-density impurity diffused region; interlevel insulating layers formed on the insulating layers and the low-density impurity diffused layers; and metal gate electrodes formed on the low-density impurity diffused layers and the interlevel insulating layers; at least one of the first high-density impurity diffused region and the second high-density impurity diffused region being arranged to overlap on active region, inward from outside edges of the active region.

Thin film transistor for antistatic circuit and method for fabricating the same

To reduce a junction leakage of an junction interface between a P type well portion formed on a P type substrate and a source region, an impurity region of a first conductive type or a second conductivity type is formed at the junction interface. A plug ion is implanted in the source region to increase a depletion depth of the source region and a counter doping is then performed in the source region to reduce an electrical field of the source region.

Method of fabricating a DRAM device

A power line and a ground line of a bipolar transistor for the electrostatic protection are isolated from a power line and a ground line of an active transistor for data input and output. Also, a resistor is coupled between a power line and a ground line of an active transistor for data input and output, and another resistor is coupled between a pad and the active transistor. Accordingly, the active transistor for data input and output is operated as an internal circuit in the electrostatic protection test since main current flows toward the bipolar transistor. An electrostatic protection circuit according to the present invention uses a bipolar transistor for the electrostatic protection and uses an active transistor for data input and output as an internal circuit in order to increase transistor size. Accordingly, a rated current of a data input and output pad is satisfied as well as the data pin capacitance is reduced since the distance between a gate and a contact in an active transistor is decreased.

Electrostatic protection circuit in a semiconductor device

A semiconductor device provide with an ESD circuit including three active regions and element isolating regions formed on a semiconductor substrate in such a manner that the active regions are isolated from one another by the element isolating regions, source/drain diffusion regions respectively formed at the active regions, a first interlayer insulating film formed on the semiconductor substrate in such a manner that it covers the active regions and element isolating regions while being provided with first contact holes for exposing the diffusion regions, first lines formed on the first interlayer insulating film in such a manner that they are electrically connected to the diffusion regions via the first contact holes, respectively, a second interlayer insulating film formed over the entire exposed surface of the resulting structure obtained after the formation of the first line in such a manner that it has second contact holes for exposing the first line disposed over a central one of the active regions, and a second line formed on the second interlayer insulating film in such a manner that it is electrically connected to the exposed first line via the second contact holes.

Field effect transistors provided with ESD circuit

A thin film transistor for an antistatic circuit includes: wells formed on a silicon substrate; insulating layers for electrical isolation between electrodes formed within the wells; low density impurity diffused regions respectively interposed between the insulating layers; a first high-density impurity diffused region formed within one low-density impurity diffused region; a second high-density impurity diffused region formed within the other low-density impurity diffused region; interlevel insulating layers formed on the insulating layers and the low-density impurity diffused layers; and metal gate electrodes formed on the low-density impurity diffused layers and the interlevel insulating layers; at least one of the first high-density impurity diffused region and the second high-density impurity diffused region being arranged to overlap an active region, inward from outside edges of the active region.

Thin film transistor for antistatic circuit and method for fabricating

A circuit for protecting against damage from an electrostatic discharge (ESD). The circuit provides protection by minimizing a voltage difference between a main voltage line and a TTL voltage line. This is accomplished with a bypass to a main ground voltage line in the case of a positive overvoltage, and a bypass to a main supply voltage line in the case of a negative overvoltage. In order to equalize the voltage between the main supply voltage line and the TTL supply voltage line, the circuit also utilizes a metal gate N-channel field transistor and a gate diode active transistor connected in parallel between the main and TTL supply voltage lines. A pair of metal gate N-channel field transistors is also connected in parallel between the main and TTL ground voltage lines in order to equalize the voltage between the main and TTL ground voltage lines.

Electrostatic discharge protection circuit

A stack capacitor capable of obtaining high capacitance in a limited area, thereby improving the integration degree of a semiconductor memory device and a process for fabricating the same. The process includes the steps of preparing a semiconductor substrate formed with a metal oxide semiconductor transistor, forming an insulating film over the transistor, forming a conductive material layer for a lower electrode plate on the insulating film such that the conductive material layer is electrically connected to the transistor, forming at least one conductive material layer for at least one additional electrode plate on the conductive material layer for the lower electrode plate such that it is spaced a predetermined distance apart from the conductive material layer for the lower electrode plate, forming at least one vertical column adapted to electrically connect the at least one additional electrode plate to the lower electrode plate, and sequentially coating a dielectric film and a plate electrode over the entire exposed surface of the resulting structure including the entire exposed surface of the additional electrode plate and the entire exposed surface of the at least one vertical column.

Method of fabricating stacked capacitor of DRAM cell

This invention relates to a method of manufacturing a MOSFET with LDD regions, high integrated semiconductor, wherein a photoresist pattern for a source/drain implant mask is formed to sufficiently cover the part where the edge between field oxide layer and LDD regions are crossed. As a result, at the place damaged from the formation of spacer at the side wall of gate electrode, high concentrated impurity should not be implanted so as to form the source/drain region within LDD regions. Consequently, this invention prevents the weakening of breakdown voltage or increase of leakage current.

Method of manufacturing a MOSFET with LDD regions

An LDD transistor, preventive of the weakening of source/drain junction breakdown voltage and the increase of junction leakage current, and a method for the fabrication of the same. The LDD transistor is comprised of: a field oxide film formed on a predetermined portion of a semiconductor having a low density ion-implanted region therein, the field oxide film having a damaged portion; a gate electrode formed over the field oxide film; an insulating film formed over the gate electrode; a gate polyoxide film resulting from the oxidation of the side wall of the gate electrode; a spacer insulating film formed at the side wall provided by the gate polyoxide film and the insulating film atop the gate polyoxide film; a pad polysilicon film deposited over the insulating film, spacer oxide film, the low density ion-implanted region and the field oxide film; and a high density ion-implanted region formed below the pad polysilicon film, being confined within the low density ion-implanted region.

Growing community of inventors

Kyoungki-do, South Korea

Jae Goan Jeong