Hynix Semiconductor Inc.

Skhynix Inc.

Kabushiki Kaisha Toshiba

Other

Jae Geun Oh

Se Aug Jang

Yong Soo Kim

Hiroaki Yoda

Tadashi Kai

Masahiko Nakayama

Masaru Toko

Choon Kun Ryu

Hyung Suk Lee

Masatoshi Yoshikawa

Yutaka Hashimoto

Keum Bum Lee

Sook Joo Kim

Hyun Chul Sohn

Min Suk Lee

Jae Sung Roh

Su-Jin Chae

Won Ki Joo

Jae Sung Rohh

Dae Gun Kang

Hyun Seok Kang

Hyun Chun Sohn

Deok Lae Ahn

A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern.

Memory device and electronic device including insulating patterns with different thermal conductivities

According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

Magnetoresistive element and method of manufacturing the same

According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metal material, a stacked body above the conductive layer, and including a first magnetization film containing a second metal material, a second magnetization film, and a tunnel barrier layer between the first magnetization film and the second magnetization film, and an insulating layer on a side face of the stacked body, and containing an oxide of the first metal material. The first magnetization film and/or the second magnetization film includes a first region positioned in a central portion, and a second region positioned in an edge portion and containing As, P, Ge, Ga, Sb, In, N, Ar, He, F, Cl, Br, I, Si, B, C, O, Zr, Tb, S, Se, or Ti.

Magnetic memory and method of manufacturing the same

Disclosed is a method for fabricating a transistor of a memory device capable of preventing voids from being created when forming a low-resistant gate electrode. The method includes the steps of forming an active area by etching a semiconductor substrate, forming a field oxide layer in the semiconductor substrate and forming a recess by etching the field oxide layer. A gate insulation layer is formed along an upper surface of the active area and an exposed portion of the active area. A gate electrode is formed on the field oxide layer such that the gate electrode extends across an upper portion of the active area while being overlapped with a channel area and the recess. The first conductive layer to be patterned has the same thickness, so the low-resistant gate electrode is easily fabricated without forming the voids.

Method of fabricating a transistor having a triple channel in a memory device

A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.

Transistor structure of memory device and method for fabricating the same

Disclosed is a method for manufacturing a transistor in a semiconductor device, which can improve a device's refresh characteristics. The method includes: providing a silicon substrate having active and field regions; performing a channel ion implantation into the substrate; sequentially forming a hard mask film and a photoresist pattern exposing a gate formation region where the channel ion implantation occurred; performing a second, higher concentration channel ion implantation using the photoresist pattern as a mask, forming doped regions in the substrate at the gate formation region and sides; etching a hard mask using the photoresist pattern as a barrier; removing the photoresist pattern; etching the substrate using a portion of the remaining hard mask as a barrier forming a groove; removing the remaining hard mask; forming a gate in the groove where the hard mask was removed; and forming source and drain regions at both sides of the gate.

Method for manufacturing transistor in semiconductor device

Growing community of inventors

Icheon-si, South Korea

Jae Geun Oh