Samsung Electronics Co., Ltd.

Jae-Eun Lee

Sunghoon Kim

Yeongkwon Ko

Teak Hoon Lee

Jaekyung Yoo

Jayeon Lee

Jin-woo Park

Jin-Woo Park

Sung-Hoon Kim

Hyang-Ja Yang

Junyeong Heo

Donghoon Won

Jae-ick Son

Hyangja Yang

Dong-Kil Yun

Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

Semiconductor package and method of fabricating the same

A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.

Semiconductor package including a first semiconductor stack and a second semiconductor stack of different widths

A method for verifying mask data in a computing device includes receiving layout data, receiving mask data, determining an interaction number between a pattern corresponding to the layout data and a pattern corresponding to the mask data, and detecting an error of the mask data based on the interaction number.

Method for verifying mask data in computing device

A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a string symbol and layout data, preparing a layout versus schematic (LVS) rule file in which a string device is defined, and performing LVS verification.

Method and system for verifying layout of integrated circuit including vertical memory cells

A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is disposed on the peripheral circuit and includes a plurality of peripheral region interconnections connecting the peripheral circuit and the plurality of cell region interconnections. The pad is disposed on the second metal layer and exchanges data, an address, or a command with the peripheral circuit during operation of the device. The second metal layer is lower than the first metal layer relative to a substrate of the device.

Nonvolatile memory device having pad structure for high speed operation

Provided are semiconductor devices including a peripheral region and a cell region stacked thereon and a method of fabricating the same. The semiconductor device may include a peripheral region including a lower substrate and a peripheral circuit provided thereon and a cell region including an upper substrate and a cell array provided thereon. The cell region may be stacked on the peripheral region. When an operation signal is applied to the cell region from the peripheral region, at least a portion of the peripheral and cell regions may be used as a ground pattern applied with a ground signal, thereby being in an electrical ground state.

Growing community of inventors

Hwaseong-si, South Korea

Jae-Eun Lee