Samsung Electronics Co., Ltd.

Jae-Duk Lee

Young-Woo Park

Jang-Gn Yun

Yoo-cheol Shin

Young-woo Park

Jae-Goo Lee

Jae-Hoon Jang

Chang-seok Kang

Jong-won Kim

Dong-Gun Park

Kohji Kanamori

Joon-Hee Lee

Jae-young Ahn

Jeong-Hyuk Choi

Jai-Hyuk Song

Young-Jin Jung

Man-Sug Kang

Bong-Hyun Kim

Sung-Yun Lee

Jung-Dal Choi

Yong-Hoon Son

Kyung-Hyun Kim

Kwang-soo Kim

Hong-soo Kim

Eun-Young Choi

Shin-Hwan Kang

Jin-taek Park

Young-Hwan Son

Phil-Ouk Nam

Yeon-Sil Sohn

Jin-I Lee

Won-Bong Jung

Kwang-Chul Park

Kanamori Kohji

Do-hyun Lee

Moo-Rym Choi

Byeong-Ju Kim

Heon-kyu Lee

Chung-Jin Kim

Yung-hwan Son

An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.

Integrated circuit device

A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

Semiconductor device

Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.

Integrated circuit devices and methods of manufacturing the same

A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

Vertical type semiconductor devices and methods of manufacturing the same

An integrated circuit device includes word line structures, insulating structures, a channel hole, and charge trap patterns. The word line structures and the insulating structures are interleaved with each other and extend in a horizontal direction parallel to a main surface of a substrate, and overlap one another in a vertical direction. The channel hole passes through the word line structures and the insulating structures in the vertical direction. The charge trap patterns are located in the channel hole, and are spaced apart from one another in the vertical direction with a local insulating region therebetween.

Integrated circuit device and method of manufacturing the same

A vertical memory device includes a substrate having a trench structure, gate electrodes on the substrate, the gate electrodes being spaced apart from each other in a first direction substantially vertical to an upper surface of the substrate, a channel including a vertical portion extending through the gate electrodes in the first direction, and a horizontal portion extending in the trench structure in a second direction substantially parallel to the upper surface of the substrate, the horizontal portion being connected the vertical portion, and an epitaxial layer on a first portion of the substrate and connected to the horizontal portion of the channel, the first portion of the substrate being adjacent to ends of the gate electrode in the second direction.

Vertical memory devices with three-dimensional channels

A vertical non-volatile memory device includes a substrate including a cell region; a lower insulating layer on the substrate; a lower wiring pattern in the cell region having a predetermined pattern and connected to the substrate through the lower insulating layer; and a plurality of vertical channel layers extending in a vertical direction with respect to a top surface of the substrate in the cell region, spaced apart from one another in a horizontal direction with respect to the top surface of the substrate, and electrically connected to the lower wiring pattern. The memory device also includes a plurality of gate electrodes stacked alternately with interlayer insulating layers in the cell region in the vertical direction along a side wall of a vertical channel layer and formed to extend in a first direction along the horizontal direction.

Vertical non-volatile memory device and method for fabricating the same

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Seongnam-si, South Korea

Jae-Duk Lee