Amkor Technology, Inc.

Amkor Technology Singapore Holding Pte. Ltd.

Jae Dong Kim

Ki Wook Lee

Robert Francis Darveaux

Miguel Angel Jimarez

Ju Hoon Yoon

Michael Barrow

Dae Keun Park

Dae Byoung Kang

Sang Jae Jang

Jin Seong Kim

Byung Joon Han

Ho Sam Choi

Choon Heung Lee

Dong Joo Park

Chul Woo Park

Kwang Ho Kim

Young Kuk Park

Sung Hwan Cho

Yeon Soo Jung

Christopher Marc Scanlan

Roger D St Amand

Jae Jin Lee

Sung Jin Yang

Min Jae Lee

Byung Jun Kim

Min Kyun Yoo

Chang Deok Lee

Jung Tae Ok

Jong Woon Choi

Jun Su Lee

In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. Other embodiments of the semiconductor device comprise one or more interposers which are electrically connected to the through-mold vias, and may be covered by the package body and/or disposed in spaced relation thereto. In yet other embodiments of the semiconductor device, the interposer may not be electrically connected to the through mold vias, but may have one or more semiconductor dies of the semiconductor device electrically connected thereto.

Semiconductor device with through-mold via

An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Exposed die overmolded flip chip package and fabrication method

A fan out build up substrate stackable package includes an electronic component having an active surface including a bond pad. A package body encloses the electronic component, the package body having a first surface coplanar with the active surface of the electronic component. A buildup dielectric layer is applied to the active surface of the electronic component and the first surface of the package body. A circuit pattern is formed within the first buildup dielectric layer and electrically connected to the bond pad, the first circuit pattern including via capture pads. Via capture pad apertures extend through the package body and expose the via capture pads. In this manner, direct connection to the first circuit pattern, i.e., the first metal layer, of the fan out build up substrate stackable package is facilitated. Further, the fan out build up substrate stackable package is extremely thin resulting in extremely thin stacked assemblies.

Fan out build up substrate stackable package and method

An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a apace between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surfaces, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Exposed die overmolded flip chip package

Exposed die overmolded flip chip package method

A circuit board has an insulative layer including a first surface and a second surface opposite to the first surface. A plurality of electrically conductive patterns is formed on the first surface of the insulative layer. Conductive lands are formed in a die mounting region of the first surface of the insulative layer and electrically connected to one of the plurality of conductive patterns on the first surface. An extending pattern extends from the conductive lands to outside of the mounting region. A protective layer covers the first surface of the insulative layer and the electrically conductive patterns. A trench is formed in the protective layer to expose the conductive lands and the extending patterns.

Circuit board and semiconductor device having the same

In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In certain embodiments, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. One or more of the semiconductor dies may include through-silicon vias formed therein for facilitating the electrical connection thereof to the conductive pattern of the substrate or to other electronic components within the vertical stack. Similarly, the semiconductor package may be provided with through-mold vias to facilitate the electrical connection thereof to other electronic components within the vertical stack. In other embodiments of the present invention, a semiconductor die which is electrically connected to the conductive pattern of the substrate is encapsulated with an inner package body which itself is formed to include through-mold vias used to facilitate the electrical connection thereof to another semiconductor die stacked thereon. In each embodiment of the semiconductor device, the vertically stacked electronic components thereof may be covered with a package body which also partially covers the substrate.

Package in package semiconductor device

A semiconductor package comprises a plurality of stacked semiconductor chips having the same structure. Therefore, the semiconductor chips can be produced using masks of the same design, resulting in a reduction in production cost and an improvement in productivity. Each of the semiconductor chips includes a plurality of through-silicon vias penetrating therethrough. The through-silicon vias of each semiconductor chip include at least one signal pad through which a common signal is delivered to the semiconductor chip and at least one chip enable pad connected to at least one chip enable pin to select the semiconductor chip. The chip enable pin may be connected to or disconnected from the chip enable pad through a conductive line to select the semiconductor chip. The conductive line is sawn to disconnect the chip enable pin from the chip enable pad before stacking of the semiconductor chip. Therefore, the semiconductor chips can be configured to have the same design, thus eliminating the need for troublesome production management and control of the semiconductor chips.

Semiconductor device

A memory card comprising a circuit board having opposed upper and lower circuit board surfaces, multiple side edges, a chamfer extending between a pair of the side edges, a plurality of pads disposed on the lower circuit board surface, and a conductive pattern which is disposed on the upper circuit board surface and electrically connected to the pads. At least one electronic circuit device is attached to the upper circuit board surface and electrically connected to the conductive pattern of the circuit board. A body at least partially encapsulates the circuit board and the electronic circuit element such that sections of the upper circuit board surface, including one which extends along the entirety of the chamfer, is not covered by the body.

Chamfered memory card module and method of making same

A memory card including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto and at least one I/O pad and at least one test pad disposed thereon. The module is inserted into a complementary cavity formed within a case of the memory card, such case generally defining the outer appearance of the memory card. The module is secured within the cavity of the case through the use of an adhesive. In each embodiment of the present invention, first and second covers are movably attached to a case for selectively covering or exposing the I/O pads and the test features/pads of the module of the memory card.

Multiple cover memory card

A wire bonding method for electrically interconnecting stacked semiconductor chips is disclosed. A substrate (e.g., printed circuit board or metal leadframe) is provided. Metal circuit patterns are provided outside of a chip mounting region of the substrate, and metal transfer patterns are provided proximate to the chip mounting region. Stacked semiconductor are disposed in the chip mounting region. Conductive wires are bonded between respective pads of one stacked chip and respective transfer patterns, and other conductive wires are bonded between respective pads of the other stacked chip and the same respective transfer patterns, thereby electrically connecting respective pads of the two chips through a pair of bond wires and an intermediate transfer pattern. The transfer patterns are separate from circuit patterns of the substrate. At least one of the first and second chips is electrically connected to some of the circuit patterns for external connection.

Wire bonding method for a semiconductor package

Growing community of inventors

Seoul, South Korea

Jae Dong Kim