Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Samsung Sdi Co., Inc.

University of Southern California

Yonsei University

Samsung Mobile Display Co., Ltd.

Bioneer Corporation

Kongju National University Industry Academia Cooperation Group

Jae Don Lee

Shi Hwa Lee

Seung Won Lee

Min Young Son

Young Sam Shin

Chae Seok Im

Min Kyu Jeong

Won Jong Lee

Jeong Joon Yoo

Choong Hun Lee

Gyu Sang Choi

Tae Wook Kang

Seok Yoon Jung

Sok Won Noh

Keun Soo Yim

Hee Jin Ahn

Jin Woo Kim

Mu Gyeom Kim

Jin Woo Park

Han Oh Park

Jung Park

Shi-hwa Lee

Hee Seok Kim

Seung Yong Song

Dong-hoon Yoo

Seong Taek Lee

Jeiwook Chae

Young Seo Choi

Sun Hoe Kim

Myung Won Song

Jin Wook Seong

Young Gil Kwon

Jin Soo Kim

Soo Jung Ryu

Jeong Wook Kim

Noh Min Kwak

Byeong Wook Yoo

Seok Joong Hwang

Chang-Woo Baek

Yeun Joo Sung

Nam Choul Yang

Youngho Ko

Sam Il Kho

Pyoung Oh Yoon

Boram Han

Young Cheol Zu

Jung Keun Park

Woon Gee Kim

Sun Gi Kim

Taewoo Kwon

Gi-Eun Choi

Dong In Kang

Mi Kyung Kang

Chae Seok Lim

A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.

Virtual architecture generating apparatus and method, and runtime system, multi-core system and methods of operating runtime system and multi-core system

The present invention relates to an oligonucleotide structure and a method for preparing the same and, more particularly, to an oligonucleotide structure in which a polymer compound is linked to an oligonucleotide via a covalent bond to improve in vivo stability of the oligonucleotide and cellular delivery efficiency of the oligonucleotide; and to a method for preparing the same. The oligonucleotide structure is improved into a homogenous material, thereby solving the problem in material verification due to polydispersion characteristics occurring when a hydrophilic material linked to the oligonucleotide is a synthetic polymer; the oligonucleotide structure is easy to synthesize compared with the existing process; and the size of a double-stranded oligo RNA structure can be accurately adjusted through the control of the repetition number of a hydrophilic material block, and thus, the gene expression regulation function of the oligonucleotide does not deteriorate through the synthesis of the optimized oligonucleotide structure, and the oligonucleotide can be delivered into cells at even a relatively low-concentration dosage. Therefore, the oligonucleotide structure of the present invention can be useful as a novel type oligonucleotide delivery system as well as a tool for treating cancers, infectious diseases, and the like.

Nanoparticle type oligonucleotide structure having high efficiency and method for preparing same

A processing apparatus for managing power based on data is provided. The processing apparatus may obtain, in response to an access request from a processor for particular data stored in a memory, existing power information having a predefined correspondence to the particular data, and control a power mode of the processor based on the existing power information.

Apparatus and method managing power based on data

A memory device may include a non-volatile memory and non-volatile RAM. The non-volatile memory may include a data block and a metadata block. Metadata information with respect to the data block may be included in the metadata block. A portion of metadata with respect to the data block or the metadata with respect to the metadata block may be stored in the non-volatile RAM.

Memory device and operating method of memory device

Provided is a method and apparatus for ray tracing. A traversal unit to process an input ray to be input among a plurality of traversal units may be determined based on age of each of the plurality of traversal units. Age of the determined traversal unit may be determined based on age of each of rays that are processed by the traversal unit.

Method and apparatus for ray tracing

A method of processing ray data the method including receiving ray data stored in input buffers; updating a property of the ray data based on a result of intersection traversal of the ray data; and outputting the ray data to an output buffer or to a feedback buffer from among the input buffers based on the updated property of the ray data. When there is insufficient space in the output buffer to store the ray data, outputting the ray data to the feedback buffer.

Ray tracing unit and method for processing ray data

A memory overlay apparatus includes an internal memory that includes a dirty bit indicating a changed memory area, a memory management unit that controls an external memory to store only changed data so that only data actually being used by a task during overlay is stored and restored, and a direct memory access (DMA) management unit that confirms the dirty bit when the task is changed and that moves a data area of the task between the internal memory and the external memory.

Apparatus and method for memory overlay

Provided is an apparatus and method for managing power based on data. The apparatus may include a code segment searching unit configured to search for at least one code segment in which a power type is inserted, a block determining unit configured to determine at least one block based on the at least one found code segment, and a power mode control unit configured to control the at least one determined block to operate in a power mode corresponding to the power type.

Apparatus and method for managing power based on data

A method for processing a three-dimensional (3D) image of a ray tracing scheme may be performed by an image processing apparatus by verifying whether local index information matching intersection point information of a ray is present within a prefetch table when intersection point information is received, and by transferring, to a shader, rendering information stored in a local memory based on the local index information, when the local index information matching the intersection point information is present.

Apparatus and method for image processing

Provided is a computing system having a hierarchical memory structure. When a data structure is allocated with respect to a task processed in the computing system, the data structure is divided and a portion of the data structure is allocated to a high speed memory of the hierarchical memory structure and a remaining data structure is allocated to a low speed memory of the hierarchical memory.

Computing system and method controlling memory of computing system

An apparatus and method for traversing a hierarchical acceleration structure may determine whether a current traversal node is a leaf node, may calculate a first distance from the current traversal node to a pop level and a second distance from a root node to the pop level when the current traversal node is the leaf node, and may determine a hierarchical traversal restarting position by comparing the first distance and the second distance.

Apparatus and method for traversing hierarchical acceleration structure

A graphic processing apparatus and method for processing ray tracing may include a plurality of traversal units to process traversal of a ray. A management unit of the graphics processing apparatus may distribute data of the ray processed by the graphics processing apparatus to the plurality of traversal units. Each of the plurality of traversal units may process ray traversal with respect to a subdivision of the entire space.

Apparatus and method for scheduling of ray tracing

An apparatus and method for detecting an error occurring when an application program is executed in a computer environment is provided. The error detection apparatus may measure a deterministic progress index (DPI) and a program counter (PC) value when an instruction is executed, set, as a verification set, a DPI and a PC value measured when the instruction is executed without causing an error, set, as a measurement set, the DPI and the PC value measured when an instruction is executed, and detect a runtime error of the instruction by comparing the measurement set to the verification set.

Apparatus and method for detecting error

A memory device includes a data block storing first data, and a log block storing second data that is an updated value of the first data. A spare area of the log block stores a first mapping table including mapping information between the first data and the second data.

Memory device and method of operation

Growing community of inventors

Paju-si, South Korea

Jae Don Lee