Samsung Techwin Co., Ltd.

Jae-chul Ryu

Chang-soo Jang

Dong-kwan Won

Hyoung-ho Roh

Seong-young Han

A method of manufacturing a multi-layer circuit layer is provided. One example method includes the steps of: preparing an upper substrate and a lower substrate, wherein each of the upper and lower substrates includes a carrier layer and a seed layer, which are detachably connected to each other; forming circuits including first circuit patterns on the upper substrate and second circuit patterns on the lower substrate by plating on the seed layer; preparing a core substrate, wherein circuit patterns comprising a conductive material are formed on the core substrate; coupling the upper substrate, the core substrate, and the lower substrate by interposing adhesive members; detaching the carrier layer from the seed layer; etching the seed layer, wherein the seed layer is removed; and electrically connecting the first circuit patterns and the second circuit patterns to the third circuit patterns, respectively.

Method of manufacturing multi-layer circuit board

A printed circuit board (PCB) and appertaining method of manufacturing are provided. The method includes: coating a metal layer on the entire surface of a substrate having an outer surface on which an interconnection pattern is formed; partially removing the metal layer from the surface of the substrate to form a window for a chip to be mounted therein and partially exposing the interconnection pattern to form a bonding finger; forming a first insulating layer on the metal layer by primarily anodizing the metal layer; electroplating a surface of the bonding finger by supplying power to the metal layer; and forming a second insulating layer disposed below the first insulating layer by entirely and secondarily anodizing the metal layer. A gold electroplating process can be performed without a lead wire, and an oxide layer formed by an anodizing process can protect circuits formed on the substrate and electrically insulate them.

Method of manufacturing a printed circuit board (PCB)

Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.

Printed circuit board and method of manufacturing the same

There are provided a printed circuit board having a structure for relieving a stress concentration on an outer most lead of leads, due to a difference in thermal expansion coefficients between the semiconductor device and the printed circuit board when the semiconductor device is mounted on the printed circuit board. The printed circuit board includes an inner lead portion to be connected to the semiconductor device. The inner lead portion includes a plurality of leads, arranged in parallel with a same pitch in a predetermined area, and additional leads located near both ends of the predetermined area in which the plurality of leads are arranged in parallel, respectively, wherein each of the plurality of leads has a pitch smaller than 30 &#x3bc;m and a width of the additional lead is wider than 20 &#x3bc;m. There are also provided a semiconductor chip package equipped with the printed circuit board according to the present invention.

Printed circuit board having structure for relieving stress concentration, and semiconductor chip package equipped with the same

A parent or master substrate for a semiconductor package is provided, which can provide a plurality of unit substrates by cutting into pieces for producing a semiconductor device. The parent substrate includes an insulation layer, conductor patterns formed on first and second surfaces of the insulation layer, and PSR (photo solder resist) layers respectively formed on the first and second surfaces of the insulation layers and covering the conductor patterns. The parent substrate includes an upper part and a lower part divided by a reference surface which passes through the center of the insulation layer. When an equivalent thermal expansion coefficient &#x3b1;of the upper part is defined by the Equation of where &#x3b1;is respective thermal expansion coefficients of, Eis respective elastic moduli of, and vis respective volume ratios of first through ncomponents constituting the upper part (e.g., insulation layer, conductor patterns, and PSR layers of the upper part), and an equivalent thermal expansion coefficient &#x3b1;of the lower part is defined by the Equation of where &#x3b1;is respective thermal expansion coefficients of, Eis respective elastic moduli of, and vis respective volume ratios of first through mcomponents constituting the lower part (e.g., insulation layer, conductor patterns, and PSR layers of the lower part), a equivalent thermal expansion ratio (&#x3b1;/&#x3b1;) of &#x3b1;to &#x3b1;is selected to be within a range of 0.975 through 1.165.

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Yongin-si, South Korea

Jae-chul Ryu