Samsung Electronics Co., Ltd.

Sungkyunkwan University

Jae-Chul Park

Young-soo Park

Sun-il Kim

Chang-jung Kim

I-hun Song

Sang-Wook Kim

Sung-ho Park

Kyoung-kook Kim

Sang-wook Kim

Yun-Ho Youm

Jun-youn Kim

Jae-cheol Lee

Taek Woon Kim

Su-hee Chae

Moon-seung Yang

Heon-Soo Lee

Young Shin Kim

Wook Su Lee

Young-Soo Park

Kee-Won Kwon

Hyung-su Jeong

Hye-Soo Lee

Jin-myoung Kim

Kyung-Ae Kim

Tong-Pyo Hong

Jae-woong Hyun

Sung-hoon Lee

Hong-mook Choi

Eun-ha Lee

Dong-hun Kang

Jong-hoon Shin

Young-jin Chung

I-Hun Song

Chae-hun Lee

Kang-Ho Lee

Jin-su Hyun

Hye-soo Lee

Kyung-Wan Nam

Ki-Seok Bae

Sun-Il Kim

Ki-won Kwon

Chung-jung Kim

Sul-il Kim

Kang-ho Lee

Chang-Jung Kim

A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.

Security devices, electronic devices and methods of operating electronic devices

Provided are an electronic system, an integrity verification device, and a method of performing an integrity verification operation. The electronic system includes: a memory device; a processor configured to provide a plurality of configuration records corresponding to a plurality of verification data stored in the memory device, each of the configuration records including a start address, a data length, and a reference hash value for a corresponding verification data; and an integrity verification device configured to: store the configuration records, select a configuration record, directly access the memory device to read verification data, corresponding to the selected configuration record, based on the start address and the data length included in the selected configuration record, perform a hash operation on the verification data to obtain a verification hash value, and output an interrupt signal based on the verification hash value and the reference hash value comprised in the selected configuration record.

Electronic system having integrity verification device

A radiation detector includes: a radiation detecting module including a photoconductive layer containing at least one heavy metal; a voltage controller configured to detect current flowing through the photoconductive layer and control application of a voltage to the photoconductive layer based on the detected current; and a sealing part configured to seal the photoconductive layer and surround a portion of the radiation detecting module.

Radiation detector and radiation imaging apparatus including the same

Provided are photon counting apparatuses and methods, and radiographic imaging apparatuses configured to receive charge signals corresponding to incident radiation photons, and to count the incident radiation photons by using a plurality of counting bits, such that the counting changes only one counting bit from among the plurality of counting bits when the count value is increased by one. By using the photon counting methods, a data-change frequency of photon counting data corresponding to radiation photons is minimized while counting the radiation photons based on charge signals corresponding to input radiation photons.

Photon counting apparatus and method, and radiographic imaging apparatus comprising the same

Disclosed is a voltage obtaining apparatus. The voltage obtaining apparatus includes a plurality of conversion units, which are connected to each other in parallel and respectively convert charge packets into voltages, and a control unit that controls a timing when the charge packets are respectively input to the plurality of conversion units. The control unit is configured to control the timing so that a corresponding charge packet is input to an nth conversion unit (where n denotes number of the conversion units) at a timing when an operation of an (n&#x2212;1)th conversion unit is ended.

Methods and apparatuses for obtaining voltage information based on charge packets input at different timings

A transistor according to example embodiments may include a channel layer, a source and a drain respectively contacting ends of the channel layer, a gate electrode separated from the channel layer, a gate insulating layer interposed between the channel layer and the gate electrode, and/or an insertion layer that is formed between the channel layer and the gate insulating layer. The insertion layer may have a work function different from that of the channel layer.

Transistor including insertion layer and channel layer with different work functions and method of manufacturing the same

A thin film transistor (TFT) may include a channel layer, a source electrode, a drain electrode, a protective layer, a gate electrode, and/or a gate insulating layer. The channel layer may include an oxide semiconductor material. The source electrode and the drain electrode may face each other on the channel layer. The protective layer may be under the source electrode and the drain electrode and/or may cover the channel layer. The gate electrode may be configured to apply an electric field to the channel layer. The gate insulating layer may be interposed between the gate electrode and the channel layer.

Thin film transistor and method of forming the same

A transistor may include: a gate insulting layer, a gate electrode formed on a bottom side of the gate insulating layer, a channel layer formed on a top side of the gate insulating layer, a source electrode that contacts a first portion of the channel layer, and a drain electrode that contacts a second portion of the channel layer. The channel layer may have a double-layer structure, including an upper layer and a lower layer. The upper layer may have a carrier concentration lower than that of the lower layer. The upper layer may be doped with a carrier acceptor in order to have an electrical resistance higher than that of the lower layer.

Thin film transistors having multi-layer channel

A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit.

Stacked memory device and method thereof

Provided is a complementary metal oxide semiconductor (CMOS) image sensor having a structure capable of increasing areas of photodiodes in unit pixels and expanding light receiving areas of the photodiodes. In the CMOS image sensor, transfer transistors may be formed on the photodiode, and reset transistors, source follower transistors, and selection transistors may be formed on a layer on which the transfer transistors are not formed. In such a CMOS image sensor, the areas of the photodiodes may be increased in unit pixels so that a size of the unit pixels may be reduced and sensitivity of the pixel may be improved.

CMOS image sensor and method of manufacturing the same

An oxide thin film transistor and a method of manufacturing the oxide TFT are provided. The oxide thin film transistor (TFT) including: a gate; a channel formed to correspond to the gate, and a capping layer having a higher work function than the channel; a gate insulator disposed between the gate and the channel; and a source and drain respectively contacting either side of the capping layer and the channel and partially on a top surface of the capping layer.

Method of manufacturing oxide thin film transistor

Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter, a NAND device, or a NOR device.

Semiconductor devices and methods of fabricating the same

Example embodiments provide a transistor and a method of manufacturing the same. The transistor may include a channel layer formed of an oxide semiconductor and a gate having a three-dimensional structure. A plurality of the transistors may be stacked in a perpendicular direction to a substrate. At least some of the plurality of transistors may be connected to each other.

Transistor and method of manufacturing the same

Provided is a channel layer for a thin film transistor, a thin film transistor and methods of forming the same. A channel layer for a thin film transistor may include IZO (indium zinc oxide) doped with a transition metal. A thin film transistor may include a gate electrode and the channel layer formed on a substrate, a gate insulating layer formed between the gate electrode and channel layer, and a source electrode and a drain electrode which contact ends of the channel layer.

Channel layer for a thin film transistor, thin film transistor including the same, and methods of manufacturing the same

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Seoul, South Korea

Jae-Chul Park