Hynix Semiconductor Inc.

Jae Chul Om

Nam Kyeong Kim

Se Jun Kim

Jae Hoon Choi

Nam-Kyeong Kim

Ga Won Lee

Sung Wook Park

Jae Hee Lee

A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.

NAND flash memory device and method of manufacturing the same

A method of manufacturing a NAND flash memory device. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.

NAND flash memory device

A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the conductive layer undergoes voltage distributions. Accordingly, a desired voltage can be applied to the blocking insulation layer, the charge trap layer and the tunnel insulating layer by controlling the effective oxide thickness (EOT) of the blocking insulation layer and the EOT of the charge trap layer and the tunnel insulating layer. It is therefore possible to improve the erase speed of a cell.

Non-volatile memory device

Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.

Method of manufacturing non-volatile memory device

A method of manufacturing a NAND flash memory device is disclosed. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.

Method of manufacturing NAND flash memory device

A method of fabricating a non-volatile memory device forming a first polysilicon film over a semiconductor substrate; forming a mitigation film over the first polysilicon film; forming a mask film over the mitigation film; etching the mask film, the mitigation film, and the first polysilicon film to form a first trench that defines first and second floating gates; forming an interlayer film over the mask film, the interlayer film filling the first trench to form a vertical structure; anisotropically etching the vertical structure of the interlayer film to form second and third trenches, the second trench being provided between the first floating gate and the etched vertical structure, the third trench being provided between the second floating gate the and etched vertical structure; forming a dielectric film over the first and second floating gate and the vertical structure, the dielectric film coating sidewalls of the second and third trenches; and forming a control gate layer over the dielectric film, the control gate layer filling the first and second trenches.

Method of fabricating flash memory device

Non-volatile memory device having SONOS structure and manufacturing method thereof

Provided is a method for manufacturing a semiconductor device including a plurality of different semiconductor elements with a transistor for fabricating the semiconductor device formed on a semiconductor substrate, an interlayer insulation film formed all over the upper part, and a hole trap site formed in the interlayer insulation film for preventing a mobile ion like H or moisture from penetrating, whereby it can be prevented that a leakage current increases abnormally where the voltage difference (Vgs) is lower than a threshold voltage.

Growing community of inventors

Kyeongki-do, South Korea

Jae Chul Om