Samsung Electronics Co., Ltd.

Jae Cheol Son

Amjad Z Qureshi

Le Trong Nguyen

Cliff Reader

Tim Lu

Mark Frederiksen

A computer system includes three processors capable to operate concurrently&mdash;a scalar processor, a vector processor, and a bitstream processor. In encoding or decoding of video data, the vector processor performs operations that can be efficiently performed by a single instruction multiple data processor, for example, a discrete cosine transform (DCT) and motion compensation. The bitstream processor performs Huffman and RLC encoding or decoding. The bitstream processor can switch contexts to enable the computer system to process several data streams concurrently. The scalar and vector processors can be programmed to execute a single arithmetic or Boolean instruction. The bitstream processor cannot be programmed to execute a single arithmetic or Boolean instruction, but can be programmed to perform an entire video data processing operation. The computer system can handle different video standards. Different Huffman encoding and decoding tables are coded to share memory. Logic is supplied to derive correct Huffman codes from the coded tables stored in the shared memory.

Methods and apparatus for processing video data

A multi-standard start code detector system receives an incoming compressed video bit stream. The compressed video bit stream includes start codes interspersed between variable length bit streams. Assuming error-free useful data, zero stuffing bits preceding a next start code are rapidly discarded on a bit group-wise basis. A group of current bits are processed by comparing them to a start code feature pattern. If a match is not detected, the entire group of bits is concurrently replaced by a next group. However, because the zero stuffing bits are of variable length, the exact position of the start code pattern is unknown. Preceding each replacement operation, the next group of bits is processed to predetect a start code feature. Upon predetecting a start code feature, the replacement operation is modified to ensure that a group of current data bits will include the start code feature pattern. This allows the number of searched for patterns to be reduced and streamlines the comparison operation. Additionally, the multi-standard start code detector system implements an error handling operation that effectively searches and discards bits on a group-wise basis. The error handling operation compares a group of current data to a pattern known to subsequently occur and that is not included in useful data. In one embodiment, the error handling operation compares the bit group to a zero stuffing bit pattern. Upon detection of the zero stuffing bits, the error handling operation proceeds in accordance with the start code feature detection operation.

Bit stream signal feature detection in a signal processing system

A group of incoming data stream bits having packed variable length code ('VLC') words is applied to an entropy code bit length searching module. The group of bits is replicated within a plurality of matching modules selectively distributed among entropy code bit length searching logic units. Each unit of entropy code bit length searching logic supports a VLC word table as characterized by, for example, standard compression formats such as MPEG-1, MPEG-2, H.261, and H.263. The matching modules are divided into groups within the entropy code bit length searching logic units. A group of matching modules is allocated to each VLC bit length represented in the associated VLC word supported table. A number of matching modules are allocated to each bit length equal to a minimum number of patterns unique to VLC words of a particular bit length. The matching modules compare an incoming data group to respective patterns. A detected match is indicated by an appropriately set group output signal. Each entropy code bit length searching logic unit includes a bit length encoder that receives the group output signals. The set group output signal indicates the bit length of a current VLC, and the bit length encoder encodes this information into a bit length code output signal. The bit length code signal is utilized by a shifter to parse a corresponding bit length of current data. The parsed current data may be directly applied to an address generator which generates an output signal for a decoding look up table.

Variable length code detection in a signal processing system

An entropy code look up table processes incoming data and provides an n-bit output signal having an entropy code word and a bit.sub.-- length output signal. Entropy code words are successively packed without spacing bits into two sixteen-bit latches. An arithmetic unit keeps track of accumulated sizes of packed, unconveyed entropy code words. The n-bit output signal is converted into a thirty-two bit signal with spacing bits on either side of a current entropy code word. Using the accumulated size information, flow through multiplexer units insert spacing bits in bit positions corresponding to bit positions currently occupied by packed entropy code words. Any remaining bits in the thirty-two bit output signal are preferably set to logical zeros. With the current entropy code word properly aligned in the thirty-two bit output signal, a path selection logic unit utilizes the accumulated size information and a unary decoder to form a sixteen bit output signal. Previously packed entropy code word(s) occupy the most significant bit(s). The remaining bit(s) are set to logical values of the current entropy code word most significant bits. These sixteen bits are written into a selected latch, and the thirty-two bit output signal least significant sixteen bits are written into the other latch. The arithmetic unit determines the number unconveyed, packed entropy code word bits. If the number is greater than fifteen, at least one of the latches is full. This number is used by the path selection logic unit to properly select the most significant latch.

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Cupertino, CA, United States of America

Jae Cheol Son