Hynix Semiconductor Inc.

Skhynix Inc.

Jae-Bum Ko

Sang-Hoon Hong

Se-Jun Kim

Jin-Hong Ahn

Sang-Jin Byeon

Chang-Ho Do

Hwang Hur

Jin-Il Chung

Jae-Hyuk Im

Young-Jun Ku

Jong-Chern Lee

Tae-Sik Yun

A buffer control circuit includes: an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal; and a buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal.

Buffer control circuit and multi-chip package including the same

A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.

Semiconductor device for parallel bit test and test method thereof

A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent semiconductor chip of the plurality of semiconductor chips, a selective setting unit suitable for generating a selective internal signal, selectively activated in each semiconductor chip, in response to the internal chip selection signal and an external setting signal, and a common setting unit suitable for generating a common internal signal, activated in common in the plurality of semiconductor chips, in response to the setting signal and an external common chip selection signal.

Semiconductor integrated circuit

A semiconductor memory device includes a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation clock in response to a first active pulse in a self-refresh operation exit mode, a second pre-charge control block suitable for generating a second control signal in response to an active command for an active operation in a self-refresh operation mode, and an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and disabling the second pre-charge control block in a self-refresh operation exit mode, wherein a pre-charge operation starts in response to the first and second control signals after the active operation. The semiconductor memory device may then be secured in a minimal time for stably performing an active operation during a self-refresh operation.

Semiconductor memory device and method for operating the same

A semiconductor device including an operation initiation block suitable for sequentially generating a plurality of operation initiation signals at a predetermined time interval in response to an operation initiation source signal, a clock-based signal generation block suitable for generating an operation termination source signal in response to one of the multiple operation initiation signals and a clock, an operation termination block suitable for sequentially generating a plurality of operation termination signals at the predetermined time interval in response to the operation termination source signal, and an operation control block suitable for sequentially generating a plurality of first operation control signals in response to the multiple operation initiation signals and the multiple operation termination signals.

Semiconductor device

A semiconductor system including a semiconductor integrated circuit or a semiconductor chip, and a method of driving the semiconductor system are described. The semiconductor integrated circuit includes a plurality of semiconductor chips, at least one first chip through via suitable for penetrating through the plurality of semiconductor chips and interfacing a source ID code between the plurality of semiconductor chips, a plurality of second chip through vias suitable for penetrating through the plurality of semiconductor chips and interfacing a plurality of chip selection signals between the plurality of semiconductor chips, wherein the semiconductor chip uses one of chip selection signals as an internal chip selection signal in response to a chip ID code by selecting one of a unique ID code for the semiconductor chip and an alternative ID code for a preset semiconductor chip when the semiconductor chip fails.

Semiconductor chip, semiconductor integrated circuit including the semiconductor chip, semiconductor system including the semiconductor integrated circuit and method of driving the semiconductor system

A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.

Semiconductor integrated circuit and semiconductor system including the same

A multi-chip package having a plurality of slice chips coupled through a through-via, at least one slice chip may include an input unit suitable for receiving a slice activation signal, and outputting the slice activation signal to the through-via in response to a slice identification corresponding to the slice chip, a first output unit suitable for outputting the activation signal transferred through the through-via to an internal circuit of the slice chip in response to the corresponding slice identification, and a second output unit suitable for selectively outputting the activation signal transferred through the through-via to the internal circuit of the slice chip in a predetermined activation mode for the multi-chip package.

Multi-chip package

A package includes a master chip including a storage circuit configured to store an impedance setting of the master chip and an impedance setting of a slave chip, and a termination circuit for an impedance matching with an outside of the package, and the slave chip connected to the master chip, wherein if a termination operation for the slave chip is activated, the termination circuit of the master chip performs an impedance matching operation using the impedance setting for the slave chip.

Semiconductor package including multiple chips and memory system having the same

An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.

Integrated circuit including semiconductor memory devices having stack structure

A semiconductor integrated circuit includes a semiconductor chip or a plurality of semiconductor chip stacked therein, wherein each semiconductor chip includes, a compatible mode selection unit configured to select a chip allocation signal allocated to the semiconductor chip, among a plurality of chip allocation signals inputted through a plurality of pads, in response to a stack package information, and an internal circuit configured to perform a given operation in response to the chip allocation signal selected by the compatible mode selection unit.

Semiconductor integraged circuit having compatible mode selection circuit

Methods for generating a refresh signal in a semiconductor device and methods for performing a refresh operation in a semiconductor memory device are disclosed. A method for generating a refresh signal includes measuring a temperature of the semiconductor memory device, generating a temperature controlled voltage based on the measured temperature, generating an N-bit digital signal based on the temperature controlled voltage, and generating a refresh signal whose frequency is determined by the N-bit digital signal. The generation of the temperature controlled voltage includes generating a first current that is increased when the measured temperature is decreased and is decreased with the measured temperature is increased, and generating the temperature controlled voltage.

Semiconductor memory device with optimum refresh cycle according to temperature variation

Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

Semiconductor memory device

A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.

Semiconductor memory device with reduced data access time

A semiconductor memory device, which performs a refresh operation, includes: a temperature sensing unit for measuring temperature and for generating a temperature controlled voltage and a reference current based on the measured temperature; an analog-digital conversion unit for converting the temperature controlled voltage to an N-bit digital signal; a refresh control unit for generating a refresh signal in response to the N-bit digital signal, wherein, a period of the refresh signal is controlled based on the N-bit digital signal.

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Ichon-shi, South Korea

Jae-Bum Ko