Skhynix Inc.

Hynix Semiconductor Inc.

Jae Boum Park

Yoon Jae Shin

Byeong Cheol Lee

Yeon Uk Kim

Young Bo Shim

Cheol Hoe Kim

Na Yeon Cho

Tae Heui Kwon

A voltage generation circuit is provided. The voltage generation circuit may include an enable signal generator, a voltage controller, and a voltage driver. The enable signal generator may generate an enable signal based on a test signal and an active signal. During activation of the enable signal, the voltage controller may compare a reference voltage with a feedback voltage, amplify the result of comparison, and generate a drive voltage. The voltage driver may output an internal voltage by driving the drive voltage, and generate the feedback voltage corresponding to the internal voltage. The feedback voltage may be pulled down during activation of the enable signal.

Circuit for generating voltage

An internal voltage control circuit according to an embodiment may include a source power supply selection unit configured to receive a first internal power supply voltage and a second internal power supply voltage and selecting the first internal power supply voltage and the second internal power supply voltage as a source voltage in response to a test mode enable signal, a first reference voltage generation unit configured to receive the source voltage from the source power supply selection unit, and configured to generate a to first low reference voltage and a first high reference voltage. The reference voltage control circuit may also include a second reference voltage generation unit configured to receive the first internal power supply voltage and configured to generate a second low reference voltage and a second high reference voltage.

Semiconductor memory apparatus, and reference voltage control circuit and internal voltage generation circuit therefor

A semiconductor memory apparatus according to the embodiment includes: an external connection terminal configured to supply an external voltage; a fuse unit configured to perform a fuse rupture operation; and an interruption circuit unit configured to respond to a test signal to determine whether the external connection terminal is connected to the fuse unit.

Semiconductor memory apparatus and method of controlling external voltage using the same

A voltage generation circuit includes: a first and second rectification circuits; and one or more amplification units connected between the first and second rectification circuits and configured to amplify an output of the first rectification circuit and provide the amplified output to the second rectification circuit. The second rectification circuit generates a reference voltage.

Voltage generation circuit

An apparatus for adjusting a resistance value of a driver of a semiconductor integrated circuit in which the resistance value of the driver is adjusted according to a code signal. The apparatus includes a control means that generates a plurality of counting mode signals such that the unit of counting is changed in a predetermined period, a counting means that counts the code signal in the unit of counting that is changed in response to the plurality of counting mode signals, according to a count up/down signal, and a comparing means that compares a voltage obtained by converting the code signal with a reference voltage to generate the count up/down signal.

Apparatus for adjusting resistance value of a driver in a semiconductor integrated circuit

A semiconductor integrated circuit includes a first buffer and a second buffer having different operational timing, a first voltage power supply for generating a first power supply voltage supplied to the first buffer in accordance with the operational timing of the first buffer, and a second voltage power supply for generating a second power supply voltage supplied to the second buffer in accordance with the operational timing of the second buffer.

Semiconductor integrated circuit

The present invention relates to a semiconductor memory device in which current consumption incurred by excessive over-driving can be prevented by dividing a memory core region into a plurality of memory blocks and then over-driving only sense amplifiers of a corresponding memory block.

Growing community of inventors

Seoul, South Korea

Jae Boum Park