Compagnie Honeywell Bull

Compagnie Honeywell Bull (societe Anonyme)

Compagnie Internationale Pour L'informatique Cii-honeywell Bull (societe

Compagnie Internationale Pour L'informatique Cii-honeywell Bull

Jacques Michel Bienvenu

Henri Verdier

Claude Carre

Duc L Tuong

Benjamin S Franklin

Jean-Claude Marcel Cassonnet

John J Bradley

Marc Michel Appell

Philippe-Hubert deRivet

Patrick Dufond

Daniel R Vinot

Robert J Bavoux

Georges Lepicard

Marcel Rene Rottier

Pierre Gabriel Antoine

Duc Luu

Michel Lecuyer

A central sub-system of a data processing system, including an operator console controlling a service processor, is divided into several sub-units, functioning separately from each other. The sub-units include processors that are connected together and to a common controller for a common memory unit by data, address and control buses. Each sub-unit includes a configuration device that stores an appurtenance indicator derived from the service processor in response to sub-unit initialization, and enables its associated sub-unit to exchange data with the memory unit. The sub-unit having the highest priority of the sub-units attempting to access the memory units is connected to the memory unit by the controller. A single configuration memory stores an indication of the sub-units in service in the central sub-system. The configuration memory is addressed each time the memory unit is addressed by a signal indicative of the appurtenance indicator derived from the selected sub-unit. The configuration memory derives an authorization signal that commands performance of memory cycles by the selected unit when the configuration memory contains an indication that the selected sub-unit is in service in the sub-system. The controller includes memorization means for storing the highest priority sub-unit trying to access the memory unit. The memorization means derives an output that is coupled to the data address and control buses to transmit a signal indicative of the number of the sub-unit with data to be exchanged with the memory unit to each of the authorizing means, thereby to establish data transmission between the sub-unit having the highest priority and the memory unit.

Device wherein a central sub-system of a data processing system is

An information structure called a semaphore serves as a signalling mechanism in process synchronization. The semaphore is used to relate a process and an event which do not appear simultaneously. In accomplishing this, the semaphore is capable of storing the presence of events or resources waiting for processes or, alternatively, the presence of processes waiting for events or resources via a queue.

Process synchronization utilizing semaphores

A method of and apparatus for executing a family of instructions provides synchronization of processes in a multiprocessing system. Representations of processes awaiting data (information units) such as the completion of an asynchronous operation or the availability of a resource are stored in a memory in a first queue and representations of information units available to processes are stored in memory in a second queue. Transfer of information units between processes is controlled by data elements known as 'semaphores' stored in the memory. Each semaphore contains a field having a numerical value identifying which of the two different kinds of queues is present. When a P instruction is executed by a process indicating that the process requires data in order to continue operating or a V instruction is executed indicating that an information unit is available for transfer to another process, a semaphore is addresses and its field tested to determine whether processes or information units are available to enable the information transfer between processes to be effected. Once the information transfer is completed, the field of the addressed semaphore is up-dated.

Apparatus and method for transferring information units between

A data processing system includes apparatus for addressing operands within a segment utilizing segment descriptors. The apparatus is responsive to instruction words executed by a first of a plurality of processes. An exemplary embodiment includes a first component which stores a segment table containing a plurality of segment descriptors, a plurality of second components, each selectively coupled to the first components and responsive to a selected one of the instruction words, identify the segment table and the location within the segment table and store an offset address within the segment identified by the segment descriptor, a third component is responsive to an address syllable element of an instruction being executed for addressing one of the plurality of second components, a fourth component stores a displacement D from the address syllable, a fifth component is coupled to the second and fourth components for adding the displacement D to the offset whereby an SRA is developed (a segment relative address), a sixth component stores an index for addressing the next sequential word following the currently addressed word and adds the index to the displacement D and to the offset, a seventh component generates an absolute address of an operand contained within the segment and is coupled to the first and fifth components for adding the segment relative address SRA to the base address of the segment descriptor associated with the segment, and an eighth component is coupled to the sixth component for incrementing the absolute address location of the operand to the next word following the currently addressed word.

Addressing of operands within a segment utilizing segment descriptors

Synchronization of processes in a multiprogramming/multiprocessing system is provided by P and V instructions that are executed during execution of processes and operate on data structures known as semaphores which represent processes and events. A process that performs P instruction requests data. The P instruction addresses a semaphore data structure stored in memory. If the semaphore indicates that the data is available, the process continues execution of its next instruction; otherwise, the process is stopped and placed into a wait state until the data become available. A process that performs a V instruction, on the other hand, delivers data to another process. The V instruction addresses a semaphore to determine whether another process is awaiting the data and data are transferred to an awaiting process. If no process is available, the V instruction enables one of the processes in the wait state tied to the same addressed semaphore to be transferred to the ready state. P and V instructions are provided for semaphore structures without messages as well as semaphore structures with messages. Each of the P and V instructions includes test instructions that enable a process to continue in the running state in the event that the test P or V instruction is unable to be executed.

Method of and system using P and V instructions on semaphores for

An information structure, or semaphore, serves as a signalling mechanism in process synchronization to connect a process and a non-simultaneously occurring event or resource. The semaphore is a data structure which stores representations of processes awaiting particular events or alternatively stores representations of events awaiting processes. Semaphore data structures are developed in two storage areas. First and second groups of process links are stored in the first storage area to establish, respectively, a first queue of processes ready to operate and a second queue, associated with the semaphore structure, of processes awaiting occurrences of a first particular event prior to being ready to operate. In the second storage area are stored first and second groups of message links to establish respectively a first queue, associated with a semaphore structure, representing second particular events and a second queue of unused links. A signal is generated in response to operation of a first process to denote the occurrence of a first event. In response to the signal, the first event is associated with a process represented by a process link in the second queue of process links when the first event is the first particular event. When no queue has a process link identifying a process awaiting the occurrence of the first event, a representation of the first event occurrence is stored in a message link of the second queue of message links to be transferred to the first queue of message links. Process and event occurrence representations are thus transferred among the process and event queues during synchronization that takes place between the processes and events.

Apparatus and method for providing synchronization between processes and

The disclosure describes improved apparatus and method for implementing the test of various computer functional units interconnected by a common bus. At the beginning of the method, each functional unit is subjected to an enforced condition which disconnects it from the bus. Then, one of the units is subjected to an enforced condition which connects it to the bus and is tested under microprogram control. After the one unit has been tested, another unit is connected to the bus and is tested. In this manner the functional units after first being disconnected from the common bus are reconnected and tested one at a time and those units which have no error detected therein are maintained connected.

Method and apparatus for implementing the test of computer functional

A multiprogrammable/multiprocessing digital computer system having a process control block for each process in the system, wherein each process control block includes information which specifies the state of a processor at any given time. Associated with each process control block is a decor extension table having information to indicate whether a specified function, such as the emulation of another processor, may be executed in the system. A native mode instruction indicating a specified function for either one instruction or for a plurality of instructions, is first checked to determine proper format, after which a determination is made by means of the decor extension table, as to whether or not the system is capable of executing the specified function indicated by the native mode instruction. If such native mode is not erroneous and if there is a positive indication of executability of the specified function by the system, then the particular specified function, such as the emulation mode of another processor, is activated.

Method and apparatus for executing an extended decor instruction

There is disclosed an input/output controller for an information processing system comprising a main memory, a central processing unit, a peripheral controller and a plurality of peripheral units coupled to the central processing unit. In particular, the input/output controller comprises a plurality of physical channels disposed between the peripheral controller and the central processing unit, a plurality of logical channels for transmitting information with the central processing unit, and each uniquely associated with one of the peripheral units. The main memory stores a first table including a physical channel entry containing informaton relative to the plurality of physical channels and a second table including a logical channel entry containing information relative to the plurality of peripheral units. Further, there is included means for storing a channel control program to be executed by the input/output control system for selectively transferring data between the main memory and the peripheral controller by first connecting the input/output control system to a logical channel entry and placing the identified logical channel table into the means for storing for a subsequent execution.

Data input and output controller

A first test and diagnosis device to check a data processing unit. The device includes means for manually testing and passing diagnostics on the first unit, as well as other means for automatically testing and diagnosing the first unit through a second data processing unit. The latter means are comprised of maintenance circuitry, contained within the first unit and linked to the second unit in such a way as to allow the second unit to conversationally interact with the first unit. This interaction is comprised of a sequence of input and output microdialogues performed by means of the maintenance circuits. The test and diagnosis microprograms may be contained in either unit.

Test and diagnosis device

Apparatus and process for the rapid processing of the data in a data processing system having a segmented memory, wherein descriptors representing the characteristics of the segments are employed in retrieving from memory and processing each segment, and wherein means is provided for the rapid locating of the descriptors for the segments most frequently utilized.

Growing community of inventors

Paris, France

Jacques Michel Bienvenu