Advanced Micro Devices Corporation

Jacques J Bertrand

George Jonathan Kluth

Minh Van Ngo

Christy Mei-Chu Woo

Paul Raymond Besser

Matthew S Buynoski

Lu You

Richard J Huang

Eric N Paton

Paul L King

Ercan Adem

John C Foster

Ramkumar Subramanian

Qi Xiang

Steven C Avanzino

Dawn M Hopper

Darin A Chan

Lynne A Okada

Simon Siu-Sing Chan

Jeffrey P Patton

Anne E Sanderfer

Yen Ching Chu

Ernesto A Gallardo

Catherine B Labelle

Barry Dick

Weiwen Ou

Shu Tsai Wang

A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.

Trenches to reduce lateral silicide growth in integrated circuit technology

Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are formed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with oxygen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.

Two-step process for nickel deposition

One aspect of the present invention relates to a system and method for mitigating surface abnormalities on a semiconductor structure. The method involves exposing the layer to a first plasma treatment in order to mitigate surface interactions between the layer and a subsequently formed photoresist without substantially etching the layer, the first plasma comprising oxygen and nitrogen; forming a patterned photoresist over the treated layer, the patterned photoresist being formed using 193 nm or lower radiation; and etching the treated layer through openings of the patterned photoresist. The system and method also includes a monitor processor for determining whether the plasma treatment has been administered and for adjusting the plasma treatment components. The monitor processor transmits a pulse, receives a reflected pulse response and analyzes the response. An optional second plasma treatment comprising nitrogen and hydrogen may be administered after the first plasma treatment but before forming the photoresist.

Effect of substrate surface treatment on 193 NM resist processing

Nickel silicidation of a gate electrode is controlled using a titanium barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of titanium thereon and an upper polycrystalline silicon layer on the titanium layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and a titanium silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.

Titanium barrier for nickel silicidation of a gate electrode

Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are fomxed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with nitrogen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.

Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by recessing the silicon nitride spacers and forming barrier spacers on top of the silicon nitride spacers. The barrier spacers prevent silicon migration and hence the formation of bridging silicide on the silicon nitride sidewall spacers.

Stacked double sidewall spacer oxide over nitride

A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.

Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.

Process for forming fully silicided gates

Nickel silicidation of a gate electrode is controlled using a cobalt barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of cobalt thereon and an upper polycrystalline silicon layer on the cobalt layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel suicide and a cobalt silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.

Cobalt barrier for nickel silicidation of a gate electrode

A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide, first and second sets sidewall spacers, and nickel silicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first set of sidewall spacers are formed from a silicon starved spacer materials, examples of which include SiO , wherein X>2, SiN , wherein X>1, or SiO N , wherein X&plus;Y>2. The second set of sidewall spacers are formed from silicon nitride and are respectively disposed adjacent the first set of sidewall spacers. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. The first set of sidewall spacers act as a silicon diffusion barrier for preventing silicon from migrating from the gate electrode to the second set of sidewall spacers. A method of manufacturing the semiconductor device is also disclosed.

Nickel silicide process using starved silicon diffusion barrier

A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide. first and second sets of sidewall spacers and nickel suicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first set of sidewall spacers are formed undoped silicon oxide and are respectively disposed adjacent the first and second sidewalls. The second set of sidewall spacers are formed from silicon nitride and are respectively disposed adjacent the first set of sidewall spacers. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. The second set of sidewall spacers being formed from undoped silicon oxide prevents the formation of nickel silicide on the second set of sidewall spacers. A method of manufacturing the semiconductor device is also disclosed.

Nickel silicide process using UDOX to prevent silicide shorting

A semiconductor device and method for manufacturing the semiconductor device employing mixed metal silicide technology is disclosed. A semiconductor device is provided having a doped silicon region, such as a source/drain. A first metal layer comprising titanium and a second metal layer comprising nickel are deposited over the semiconductor device. The device is subjected to rapid thermal annealing. The resulting device has a mixed metal silicide layer over the doped silicon region, the mixed metal silicide layer and the doped silicon region having smooth interface between them.

Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface

A method for manufacturing a semiconductor device employing mixed metal silicide technology is disclosed. The method comprises providing a semiconductor device having a doped silicon region, such as a source/drain, sequentially layering a first metal comprising cobalt, and a second layer comprising nickel over the semiconductor device, and subjecting the device to rapid thermal annealing. The resulting device has a mixed metal silicide layer overtop the doped silicon region, wherein the mixed metal silicide layer and the doped silicon region form a smooth boundary between them.

Dual layer nickel deposition using a cobalt barrier to reduce surface roughness at silicide/junction interface

Nickel silicidation of a gate electrode is controlled using a tungsten silicide barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of tungsten silicide thereon and an upper polycrystalline silicon layer on the tungsten silicide layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and the tungsten silicide barrier layer prevents nickel from reacting with the lower polycrystalline silicon layer.

Tungsten silicide barrier for nickel silicidation of a gate electrode

A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; forming nickel silicide layers disposed on the source/drain regions and the gate electrode, and two etching steps. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600&deg; C. The first etch is performed with a sulfuric peroxide mix to remove unreacted nickel, and the second etch is performed with an ammonia peroxide mix to remove nickel silicide formed over the first and second sidewall spacers.

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Capitola, CA, United States of America

Jacques J Bertrand