University of Washington

Jacques Christophe Rudell

Thomas K Lewellen

David Allstot

Eric Pepin

Parmoon Seddighrad

Tong Zhang

Apsara Ravish Suvarna

Samrat Dey

An input driven self-clocked dynamic comparator, and associated systems and methods are described herein. In one embodiment, self-clocked dynamic comparator, includes a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT−) signal. The self-clocked dynamic comparator also includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF. The self-clocked dynamic comparator further includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF, and a logic gate configured to receive the TRI signal and one of the OUT+ signal and OUT− signal, and configured to output the CLKsf signal. The cycles of the CLKsf signal cause the latch to dissipate energy.

Input driven self-clocked dynamic comparator

Front-end analog circuitry is described based on a sink-regulated H-bridge topology for delivery of biphasic stimulus signals that may be useful in neurostimulation. Stimulus current may be supplied using fully-integrated dynamic voltage supplies (DVSs), which may be controlled in closed-loop to have an output voltage approximately equal to the voltage of the electrode each supplies stimulus to. The stimulus waveform may be regulated by a single, low-voltage current-digital-to-analog converter (current-DAC), which can safely interface with the electrodes (which may be at high voltages) via high-voltage adapter (HVA) circuits. Example analog front-end circuitry may utilize the balancing stimulus current to discharge the electrode-tissue interface impedance (Z). In some examples, only after full (or sufficient) Zdischarge has been detected is a DVS used to supply the remaining balancing stimulus.

Analog front-end circuitry for biphasic stimulus signal delivery finding use in neural stimulation

Example apparatuses and methods for cancellation of transmitter self-interference leakage in a transceiver are described. An example transceiver includes a multiport transformer that may be used as a part of the impedance matching network on the receiver side of the transceiver. One primary port of the multiport transformer may form a portion of a cancellation circuit that, along with other components in a cancellation path, provide amplitude and/or phase modulation to a cancellation signal. The cancellation circuit may tunable and may include only reactive components in some examples.

Systems, transceivers, receivers, and methods including cancellation circuits having multiport transformers

A harmonic-rejection power amplifier is disclosed. In an embodiment, the harmonic-rejection power amplifier includes a plurality of stages, each stage comprising a respective signal-generation component coupled to a respective power amplifier, wherein the respective signal-generation component is configured to output a respective signal having a respective phase, and wherein the respective power amplifier is configured to output an amplified version of the respective signal. In the harmonic-rejection power amplifier, each respective phase differs from each other respective phase by a respective amount that is predefined based on a number of stages in the plurality of stages, and the plurality of stages are coupled in parallel to a combiner configured to combine the output of each respective power amplifier into a combined output. At least one harmonic in the combined output may be at least partially rejected.

Growing community of inventors

Seattle, WA, United States of America

Jacques Christophe Rudell