Microchip Technology Inc.

Jacobus Albertus Van Eeden

Yong Yuenyongsgool

Joseph Harry Julicher

Sean Steedman

Keith Edwin Curtis

Kevin L Kilzer

Prashanth Pulipaka

Naveen Raj

David Otten

David Martin

Prasanna Surakanti

Marilena Dracea

Michael Garbutt

An embedded system and method for controlling such are disclosed. The embedded system includes a direct memory controller comprising a plurality of channels, wherein a plurality of channel arbitration schemes are programmable, wherein the DMA controller is programmable to split a block data transfer on a specified channel into a plurality of separate data transfers, wherein a data transfer on a specified channel can be interrupted between separate data transfers of the data transfer.

Method and apparatus for split burst bandwidth arbitration

A three input voltage comparator provides termination of a pulse width modulation (PWM) output in a switched mode power supply. Shutdown of the PWM signal occurs when a sense current from the switching transistors exceeds either or both of the limit and error current references. The three input voltage comparator replaces the generally used two input voltage comparator and also eliminates the necessity of having to provide a voltage clamping circuit on the output of the voltage error amplifier in the switched mode power supply. The three input voltage comparator may also comprise selectable polarity control for more versatile integration of it into a switched mode power supply design.

Three input comparator

A digitally controlled ramp generator has a constant current source, a first controllable switch coupled between the constant current source and an output node, a capacitor coupled with the output node, a second controllable switch coupled with the output node, a constant current sink coupled with the second controllable switch, and a control unit. The control unit is configured in a first operating mode to select control signals for the first and second controllable switch to generate a rising waveform by charging said capacitor through the first controllable switch and a falling waveform by discharging the capacitor through the second controllable switch wherein the control signals can be selected from the group of a time based control signal and a voltage based control signal. A variety of other control modes may be provided.

Ramp generation module

A method for expanding a data memory for a microprocessor architecture which uses a bank select accessing scheme for accessing data memory which is divided into a plurality of memory banks. A bank select register is configured to select a memory bank and the microprocessor architecture has an instruction set with a dedicated instruction for selecting a memory bank. An opcode of the dedicated bank select instruction provides for a maximum of n bits payload thereby providing for an address value which is configured to select a maximum of 2memory banks. The method has the steps of: using an opcode of a test instruction that provides for m bits of payload for a new bank select instruction, wherein m&#x3e;n; and using an opcode of the dedicated bank select instruction for a new test instruction.

Method for enlarging data memory in an existing microprocessor architecture with limited memory addressing

A pulse width modulator has a first clock source providing a clock signal to a set input of an output controller configured to set a pulse width output signal and having a reset input to reset the pulse width output signal. A duty cycle control unit is coupled with the reset input of the output controller, wherein the duty cycle control unit has a numerical controlled oscillator (NCO) being coupled with a register and configured to provide for a direct digital synthesis to produce a specified frequency according to a value set in the register. Furthermore, logic is provided for receiving a signal from a second clock source and the pulse width output signal to trigger the numerical controlled oscillator.

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Chandler, AZ, United States of America

Jacobus Albertus Van Eeden