Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Sandisk Enterprise IP LLC

Smart Storage Systems, Inc.

Jacob Schmier

Robert W Ellis

Kevin M O'Toole

Todd Lindberg

Mervyn Wongso

Lakshmana Chintada

Rushang Karia

Kevin Corbin

James M Higgins

Mark Joseph Dancho

Ryan R Jones

Atif Hussain

Venugopal Garuda

Edoardo Daelli

Andrew David Prosory

Aspects of a storage device including a memory and a controller are provided which allow for detection of dropped commands based on a die status (ready/busy status) of a command received from a host device. The memory may include dies controlled by chip-enables (CE). After selecting a die using CE, the controller waits between a minimum and maximum time after receiving the command to query the die status, where the minimum time is the time by which the command is expected to begin execution and the maximum time is the shortest time by which the command is expected to complete execution. The controller queries the die status after waiting the time period. If the die status is ready when it should have read busy, the controller detects that the command associated with the data is dropped and requests the host device to reissue the command.

NAND dropped command detection and recovery

A method and apparatus is disclosed for using supervised learning with closed loop feedback to improvement of output consistency for memory arrangements, such as a solid state drive.

Supervised learning with closed loop feedback to improve input output consistency of solid state drives

Aspects of a storage device including a memory and a controller are provided which prevent retransmissions of set features commands with identical read voltage threshold offsets for the same die. When the controller receives a first read command for data stored in the memory, the controller identifies a first parameter to modify a first read threshold, and executes a first set features command for modifying the read threshold based on the first parameter. Subsequently, when the controller receives a second read command from the host device for data stored in the memory, the controller identifies a second parameter to modify a second read threshold, and determines whether the first and second parameters are the same. If the parameters are the same, the controller refrains from executing a second set features command for modifying the second read threshold. Thus, the read latency of the storage device may be reduced.

Command optimization through intelligent threshold detection

A non-volatile memory (NVM) system receives host requests that each specify a memory operation to be performed by the NVM system, the specified memory operations including read operations and write operations, and performs a set of operations for each memory operation specified by a received host request. The set of operations performed for each such memory operation include: initiating performance the memory operation; determining a throttle interval for the memory operation in accordance with at least a first factor, corresponding to available space in a write cache of the non-volatile memory system, and a second factor, corresponding to a metric corresponding to prevalence of write operations in the memory operations specified by the received host requests; and returning to the host system a response associated with the memory operation at a time no earlier than a start time associated with the memory operation plus the determined throttle interval.

Method and system for input-output throttling to improve quality of service in a solid state drive

A memory system comprises a plurality of memory dies and a controller (or other control circuit) connected to the memory dies. To reduce the time it takes for the memory system to program data and make that programmed data available for reading by a host (or other entity), as well as persistently store the data in a compact manner that efficiently uses space in the memory system, the data is concurrently programmed as single bit per memory cell (fast programming) and multiple bits per memory cell (compact storage). To accomplish this programming strategy, the controller concurrently transfers data to be programmed to a first memory die and a second memory die. The transferred data is programmed in the first memory die at a single bit per memory cell and in the second memory die at multiple bits per memory cell.

Non-volatile storage system with reduced program transfers

Supervised learning with closed loop feedback to improve ioconsistency of solid state drives

In a non-volatile memory system, a fast bulk secure erase method for erasing data includes, in response to a secure erase command: applying charge to a portion of non-volatile memory in the non-volatile memory system, and performing an erase operation sufficient to remove charge from the portion of non-volatile memory to below an erase threshold. The applied charge is sufficient to program memory cells in the portion of non-volatile memory to above a pre-erase program threshold.

Secure erase of non-volatile memory

The various implementations described herein include systems, methods and/or devices used to validate the status of memory operations in a storage device. In one aspect, the method includes sending a first set of command instructions to a first device of the plurality of non-volatile memory devices, including: a memory operation command; a first status polling command to determine a status of the first device, and a second status polling command to determine a status of the first device. The first status polling command is sent after the memory operation command is sent, and the second status polling command is sent after receiving a response to the first status polling command that meets predefined completion criteria. The method further includes forgoing sending any subsequent set of command instructions to the first device until a response to the second status polling command that meets the predefined completion criteria is received.

Validating the status of memory operations

A method of operation of a storage control system includes: calculating a throttle threshold; identifying a detection point based on the throttle threshold; and calculating a number of write/erase cycles based on the detection point and the throttle threshold for writing a memory device.

Storage control system with data management mechanism and method of operation thereof

The various implementations described herein include systems, methods and/or devices used to enable power failure tolerant cryptographic erasure in a storage device having a first encryption key established as a current encryption key. The method includes performing a set of first stage operations including selecting first and second sets of memory blocks and obtaining a second encryption key. The method includes performing a set of second stage operations including storing, in the first set of memory blocks, first and second sets of metadata, encrypted using the second encryption key. The method includes performing a set of third stage operations, including storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key. The method includes setting the second encryption key as the current encryption key for the plurality of memory blocks.

Growing community of inventors

Gilbert, AZ, United States of America

Jacob Schmier