Intel Corporation

Jacob M Jensen

Tahir Ghani

Harold W Kennel

Mark Y Liu

Robert G James

Mark L Doczy

Markus Kuhn

John P Barnak

Collin Borla

Anand S Murthy

Patrick R Morrow

Glenn A Glass

Paul B Fischer

Kimin Jun

Chandra S Mohapatra

Karthik Jambunathan

Daniel Bourne Aubertine

Tensile strain is applied to a channel region of a transistor by depositing an amorphous SiGeCalloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SiGeCalloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.

Crystallized silicon carbon replacement material for NMOS source/drain regions

A method including coupling a device substrate to a carrier substrate; aligning a portion of the device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and after separating the portion of the device substrate, coupling the portion of the device substrate to the host substrate. A method including coupling a device substrate to a carrier substrate with an adhesive between a device side of the device substrate and the carrier substrate; after coupling the device substrate to the carrier substrate, thinning the device substrate; aligning a portion of the thinned device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and coupling the separated portion of the device substrate to the host substrate. An apparatus including a substrate including a submicron thickness and a device layer coupled to a host substrate in a stacked arrangement.

Heterogeneous integration of ultrathin functional block by solid phase adhesive and selective transfer

A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

Pulsed laser anneal process for transistor with partial melt of a raised source-drain

Pulsed laser anneal process for transistors with partial melt of a raised source-drain

A pulsed-laser anneal technique includes performing an implant of a selected region of a semiconductor wafer. A co-constituent implant of the selected region is performed, and the pulsed-laser anneal of the selected region performed. A pre-amorphizing implant of the selected region can also be performed. In one embodiment, the implant of the selected region is performed as an insitu implant. In another embodiment, the co-constituent implant is performed as an insitu non-donor implant. In yet another embodiment, the implant and the co-constituent implant of the selected region are performed as an insitu donor and co-constituent implant.

Method for forming superactive deactivation-resistant junction with laser anneal and multiple implants

Laser anneal to melt regions of a microelectronic device buried under overlying materials, such as an interlayer dielectric (ILD). Melting temperature differentiation is employed to selectively melt a buried region. In embodiments a buried region is at least one of a gate electrode and a source/drain region. Laser anneal may be performed after contact formation with contact metal coupling energy into the buried layer for the anneal.

Selective laser annealing process for buried regions in a MOS device

A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or 'tuned' depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.

Methods of forming a multilayer stack alloy for work function engineering

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Beaverton, OR, United States of America

Jacob M Jensen