Intel Corporation

Jacob Jun Pan

Vincent J Zimmer

Ashok Raj

Srinivas Pandruvada

Apparatus, method, and machine-readable medium to provide performance state matching between source and target processors based on inter-processor interrupts. An exemplary apparatus includes a target processor to execute a receiving task at a first performance level and a source processor to execute a sending task at a second performance level higher than the first performance level. The sending task is to store interrupt routing data indicating a pairing between the sending task and the receiving task into a memory location and that the sending task is to dispatch work to be processed by the receiving task. The apparatus further includes a performance management unit to detect the pairing between the sending task and the receiving task based on the interrupt routing data and responsively adjust the performance level of the target processor from the first performance level to the second performance level based, at least in part, on the pairing.

Apparatus and method for performance state matching between source and target processors based on interprocessor interrupts

In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

Management of processor performance based on user interrupts

In some embodiments, the invention involves a dynamic interrupt route discovery method with local APIC (Advanced Programmable Interrupt Controller) retriggering to accommodate architectures that are not PC/AT compatible. In a low power mobile device, General Purpose Input/Output (GPIO) pins are dynamically allocated and IRQs are retriggered by a GPIO driver to multiplex the requests to an appropriate device. Other embodiments are described and claimed.

System and method for dynamic, local retriggered interrupt routing discovery

In some embodiments, the invention involves a dynamic interrupt route discovery method with local APIC (Advanced Programmable Interrupt Controller) retriggering to accommodate architectures that are not PC/AT compatible. In a mobile Internet device (MID) General Purpose Input/Output (GPIO) pins are dynamically allocated and IRQs are retriggered by a GPIO driver to multiplex the requests to an appropriate device. Other embodiments are described and claimed.

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Portland, OR, United States of America

Jacob Jun Pan