Ampere Computing LLC

Jacob Daniel Morgan

Benjamin C Chaffin

Jonathan Christopher Perry

Bret Leslie Toll

Sean Philip Mirkes

Jason Anthony Bessette

Michael Spradling

John Saint Tran

David Nuechterlein

A compute node capable of enhanced performance and/or energy savings is proposed. The proposed compute node may check whether a last instruction of a first group—retrieved in a first decode cycle—is potentially a fusible instruction. If so, the proposed compute node may refrain from decoding the last instruction in the first decode cycle. Instead, the proposed compute node may determine if a first instruction of a second group of instructions retrieved in a second decode cycle (subsequent to the first decode cycle) is fusible with the last instruction of the first group. If so, the two instructions may be fused to a single micro-operation.

Mechanism for instruction fusion

Aspects disclosed include hardware micro-fused memory (e.g., load and store) operations. In one aspect, a hardware micro-fused memory operation is a single atomic memory operation performed using a plurality of data register operands, for example a load pair or store pair operation. The load pair or store pair operation is treated as two separate operations for purposes of renaming, but is scheduled as a single micro-operation having two data register operands. The load or store pair operation is then performed atomically.

Hardware micro-fused memory operations

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Forest Grove, OR, United States of America

Jacob Daniel Morgan