Micron Technology Incorporated

International Business Machines Corporation

Jacob D Sloat

Stephen P Glancy

Cyrus Elmtalab

Kyu-hyoun Kim

Saravanan Sethuraman

Anuwat Saetow

Paul William Rudrud

John Stanley Bialas, Jr

Jeremy R Neaton

A method includes determining, by a first component of a memory sub-system controller, a first temperature value of the memory subsystem controller. The method can further include determining, by a second component of a non-volatile memory device, a second temperature value of the non-volatile memory device coupled to the memory sub-system controller. The method can further include modifying a data parameter in response to at least one of the first temperature value or the second temperature value exceeding a threshold temperature value.

Memory sub-system temperature regulation by modifying a data parameter

A controller of a non-volatile, dual, in-line memory modules (NVDIMM). A NVDIMM is configured to predict thermal events associated with save and restore operations prior to starting the save or restore operation. The controller of the NVDIMM includes a thermal event prediction circuit to predict whether a thermal event will occur in response to a request to perform a save or restore operation, and to cause the controller to perform an action in response to a determination that a thermal event is likely to occur. To predict the thermal event, the controller may be configured to predict a peak temperature of the save or restore operation based on a predicted temperature increase from an initial or starting temperature. The predicted temperature increase may be based on a rate of temperature change during the save or restore operation and a duration of the save or restore operation.

Thermal event prediction in hybrid memory modules

Methods, apparatuses, and systems related to a memory device are described. A controller may be configured to predict a temperature of a memory based on a real-time temperature of the controller. Based on the predicted temperature of the memory, the controller may execute a remedial action to reduce an actual temperature of the memory for executing an upcoming operation.

Apparatus with temperature mitigation mechanism and methods for operating the same

Methods, apparatuses, and systems related to a memory device are described. The memory device may include a non-volatile (NV) memory and a controller. The controller may be configured to predict a temperature of the NV memory based on a real-time temperature of the controller. Based on the predicted temperature of the NV memory, the controller may execute a remedial action to reduce an actual temperature of the NV memory for executing an upcoming operation.

Memory sub-system temperature regulation

In an example, a system includes a memory controller that includes a plurality of memory components. The system also includes a memory controller configured to receive a plurality of memory settings to be applied to the plurality of memory components. The memory controller is configured to, based on the received memory settings, transmit a first command to the plurality of memory components, the first command causing each memory component of the plurality of memory components to be configured to a first memory setting. The memory controller is configured to, based on the received memory settings, transmit a second command to a subset of the plurality of memory components after transmitting the first command, the second command causing each memory component of the subset to be configured to a second memory setting.

Efficient configuration of memory components

A method, system and memory controller are provided for implementing signal integrity fail recovery and mainline calibration for Dynamic Random Access Memory (DRAM). After identifying a failed DRAM, the DRAM is marked as bad and taken out of mainline operation. Characterization tests and periodic calibrations are run to evaluate optimal settings and to determine if the marked DRAM is recoverable. If recoverable, the marked DRAM chip is redeployed. If unrecoverable, error reporting is provided to the user.

Implementing signal integrity fail recovery and mainline calibration for DRAM

Correction of duty cycle distortion of DQ and DQS signals between a memory controller and a memory is corrected by determining a duty cycle correction factor. The duty cycle distortion is corrected by applying the duty cycle correction factor to the plurality of differential DQS signals. The duty cycle distortion is corrected across a plurality of differential DQS signals between the memory controller and the bursting memory.

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Rochester, MN, United States of America

Jacob D Sloat