Advanced Micro Devices Corporation

Sandisk Corporation

Aurora Systems, Inc.

Vlsi Technology, Inc.

Philips Electronics North America Corporation

Xerox Corporation

Jacob D Haskell

Jack H Yuan

Steven C Avanzino

Subhash Gupta

Craig S Sander

Rong Hsu

Calvin T Gabriel

Satyendra S Sethi

Subhas Bothra

Donald L Wollesen

Balaji Swaminathan

Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called 'shallow trench isolation' or 'STI.' Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming

Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called 'shallow trench isolation' or 'STI.' Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the columm direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Method of forming non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors

Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called &ldquo;shallow trench isolation&rdquo; or &ldquo;STI.&rdquo; Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

A combination CMP-etch method for forming a thin planar layer over the surface of a device includes the steps of providing a substrate including a plurality of surface projections defining gaps therebetween, forming an etchable layer on the substrate, performing a CMP process on the etchable layer to form a planar layer having a first thickness in excess of 1,000 Angstroms, and etching the planar layer to a second thickness less than 1,000 Angstroms. In a particular method, the step of forming the etchable layer includes the steps of forming an etch resistant layer on the substrate, forming a fill layer on the etch-resistant layer, etching the fill layer to expose portions of the etch-resistant layer overlying the projections, and to leave a portion of the fill layer in the gaps, and forming the etchable layer on the exposed portions of the etch-resistant layer and the fill layer.

Combination CMP-etch method for forming a thin planar layer over the surface of a device

The present invention relates to semiconductor devices in general, and more particularly to semiconductor devices having anti-reflective coatings to aid in the patterning of a reflective layer thereon to form, for example, a gate electrode. The invention also relates to methods for making a semiconductor having a patterned reflective layer.

Sacrificial multilayer anti-reflective coating for mos gate formation

A method for manufacturing a planar reflective light valve backplane includes the steps of providing a substrate (e.g., a reflective backplane) including a plurality of surface projections (e.g., pixel mirrors) defining gaps therebetween, forming an etch-resistant layer on the substrate, forming a fill layer on the etch resistant layer, and etching the fill layer to expose portions of the etch resistant layer overlying the projections, leaving a portion of the fill layer in the gaps. A particular method includes an optional step of forming a protective layer over the exposed portions of the etch-resistant layer and the fill layer. In another particular method, the etch resistant layer includes an optical thin film layer and an etch-resistant cap layer.

Method for manufacturing a planar reflective light valve backplane

A planar wafer based device (e.g., a reflective light valve backplane) includes a substrate having a plurality of surface projections (e.g., pixel mirrors) defining gaps therebetween, an etch-resistant layer formed on the substrate, and a fill layer formed on a portion of the etch-resistant layer in the gaps. In a particular embodiment, the fill layer is a spin-on coating. An optional protective layer formed on the exposed portions of the etch-resistant layer and the fill layer protects the underlying layers during subsequent processing steps.

Planar reflective light valve backplane

Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a conductive via metallization layer over the etch stop layer. Forming a hard mask layer over the conductive via metallization layer. The process further includes producing a conductive via and an interconnect line, where the conductive via is formed from a portion of the conductive via metallization layer, and the interconnect line is formed from a portion of the first interconnect metallization layer. The conductive via is substantially aligned with the underlying interconnect line.

Process for making self-aligned conductive via structures

According to one aspect of the invention, a method of fabricating N+ and P+ silicided gates limits diffusion when using a Tungsten, Titanium or Cobalt silicide in the gate fabrication. An example method involves doping a polysilicon structure in first and second dual gate regions and on either side of an undoped polysilicon region, forming a silicide is over the polysilicon structure, and then stuffing the undoped polysilicon region with a species selected to inhibit lateral diffusion of dopant from the polysilicon in the silicide. Subsequently, each gate is completed so that is includes a dielectric layer arranged over the silicide and one of the doped gate poly regions. Applications include logic circuits having embedded-DRAM, and circuits directed to stand-alone logic or stand-alone DRAM.

Semiconductor device with gate electrodes for sub-micron applications

A method for fabricating a semiconductor integrated circuit structure having a reduced width gate electrode. A pre-gate electrode having a width is first delineated by conventional lithography techniques. The conductive layer is partially etched to expose a first and second pre-gate side wall. With the pre-gate side walls exposed, the structure is oxidized to grow an oxide layer on the pre-gate side walls, thereby consuming a predetermined amount of the conductive material. The newly formed oxide layer is then removed to reduce the pre-gate width while retaining at least a portion of an oxide layer above the conductive layer as a mask. The reduced width gate electrode is completed by etching the remaining unmasked conductive layer.

Method for forming a reduced width gate electrode

An etch stop layer (22) for permitting distinguishing between two similar layers (20, 24), such as two oxide layers, during etching is provided. The etch stop layer comprises a silicon-oxyhalide polymer, preferably a silicon-oxyfluoride polymer. Use of the polymer as an etch stop layer permits closer placement of metal conductor surfaces (12, 12') and contacts (14').

Etch stop layer using polymers for integrated circuits

An etch stop player (22) for permitting distinguishing between two similar layers (20, 24), such as two oxide layers, during etching is provided. The etch stop layer comprises a silicon-oxyhalide polymer, preferably a silicon-oxyfluoride polymer. Use of the polymer as an etch stop layer permits closer placement of metal conductor surfaces (12, 12') and contacts (14').

Etch stop layer using polymers

A low resistance interconnect structure for integrated circuits formed by a composite layer of aluminum below and an amorphous compound of refractory metal and silicon above. In the process of manufacturing the interconnect structure, care must be taken so that an aluminum oxide layer is not formed between the aluminum and compound layers.

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Palo Alto, CA, United States of America

Jacob D Haskell