Taiwan Semiconductor Manufacturing Comp. Ltd.

Nxp B.v.

Koninklijke Philips Corporation N.v.

Interuniversitair Microelektronica Centrum (Imec)

Jacob Christopher Hooker

Robert James Lander

Markus Mueller

Marcus Johannes Henricus Van Dal

Youri Victorovitch Ponomarev

Robertus Adrianus Maria Wolters

Robertus Theodorus Fransiscus Van Schaijk

Tom Schram

Michiel Jos Van Duuren

Raghunath Singanamalla

Jasmine Petry

Robertus Wolters

A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a first type of conductivity, a second channel region formed in a second portion of the substrate and being doped with a dopant of a second type of conductivity, a gate insulating layer formed on the first channel region and on the second channel region, a dielectric capping layer formed on the gate insulating layer, a first gate region formed on the dielectric capping layer over the first channel region, and a second gate region formed on the dielectric capping layer over the second channel region, wherein the first gate region and the second gate region are made of the same material, and wherein one of the first gate region and the second gate region comprises an ion implantation.

Transistor device and a method of manufacturing same

The present disclosure provides a semiconductor device that includes a semiconductor substrate having a first region and a second region, a pMOS transistor formed over the first region and an nMOS formed over the second region. The pMOS transistor has a gate structure that includes: an interfacial layer formed over the substrate; a AlOlayer formed over the interfacial layer; and a metal layer including Mo or W formed over the AlOlayer. The nMOS transistor has a gate structure that includes: the interfacial layer formed over the substrate; a DyOlayer formed over the interfacial layer; and the metal layer including Mo or W formed over the DyOlayer.

Single metal dual dielectric CMOS device

Transistor device and a method of manufacturing the same

A method is provided of manufacturing a semiconductor device comprising a first, n-type field effect transistor () and a second, p-type field effect transistor (). The method comprises depositing a gate dielectric layer over a substrate; depositing a gate metal layer () over the gate dielectric layer, depositing a solid metal oxide layer () over the gate dielectric layer; removing a portion of the solid metal oxide layer () over an area of the substrate corresponding to the n-type transistor; and completing gate stacks for the n-type and p-type transistors and forming source and drain regions. The invention thus provides a device which is compatible with IC technology and easy to manufacture. The deposition of a solid metal oxide layer provides a simplified manufacturing process, by avoiding the complexity of gas exposure to form an oxide layer.

Complementary semiconductor device with a metal oxide layer exclusive to one conductivity type

The invention relates to a CMOS device () with an NMOST I and PMOSThaving gate regions (D,D) comprising a compound containing both a metal and a further element. According to the invention the first and second conducting material both comprise a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and both comprise as the further element an element selected from the group comprising carbon, oxygen and the chalcogenides. Preferably both the first and second conducting material comprise a compound of molybdenum and carbon or oxygen. The invention also provides an attractive method of manufacturing such a device.

Semiconductor device and method of manufacturing such a semiconductor device

In the method for manufacturing a semiconductor device (), which comprises a semiconducting body () having a surface () with a source region () and a drain region () defining a channel direction () and a channel region (), a first stack () of layers on top of the channel region (), the first stack () comprising, in this order, a tunnel dielectric layer (), a charge storage layer () for storing an electric charge and a control gate layer (), and a second stack () of layers on top of the channel region () directly adjacent to the first stack () in the channel direction (), the second stack () comprising an access gate layer () electrically insulated from the semiconducting body () and from the first stack (), initially a first sacrificial layer () is used, which is later replaced by the control gate layer (). A second sacrificial layer () is used to protect the part () off the surface () adjacent to the second sidewall () and opposite to the position () of the second stack () when providing the access gate layer ().

Method of manufacturing a semiconductor device

Consistent with an example embodiment, a method of manufacturing a semiconductor device comprises MOS transistors having gate electrodes formed in a number of metal layers deposited upon one another. Active silicon regions having a layer of a gate dielectric and field-isolation regions insulating these regions from each other are formed in a silicon body. Then, a layer of a first metal is deposited in which locally, in a part of the active regions, nitrogen is introduced. On the layer of the first metal, a layer of a second metal is then deposited, after which the gate electrodes are etched in the metal layers. Before nitrogen is introduced into the first metal layer, an auxiliary layer of a third metal permeable to nitrogen is deposited an the first metal layer. Thus, the first metal layer can be nitrided locally without the risk of damaging the underlying gate dielectric.

Method of manufacturing MOS transistors with gate electrodes formed in a packet of metal layers deposited upon one another

A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed. In one embodiment, the method includes i) forming, at least at the silicon region, a metal cluster layer from a first metal, such that, in the metal cluster layer, metal clusters alternate with sites where there are no metal clusters, the first metal being a non-siliciding metal at predetermined conditions, ii) depositing a metal layer of a second metal on top of the metal cluster layer, the second metal being a siliciding metal and iii) carrying out at least one heat treatment at the predetermined conditions on the second metal layer so as to form metal silicide through reaction of the second metal with the silicon region, wherein atoms of the first metal are displaced in a direction substantially perpendicular to the surface of the substrate.

Semiconductor device fabricated by a method of reducing the contact resistance of the connection regions

The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide. In one embodiment, those parts of the conductors which have different work functions are formed by etching a layer other than the silicon layer, in particular a metal layer, at the location of one of the two semiconductor structures. Furthermore, a further metal layer is applied over the silicon layer and is used to form a further metal silicide at the location of the second transistor. One embodiment of the invention is particularly suitable for use in CMOS technology and results in both PMOS and NMOS transistors with favorable properties.

Method for fabricating semiconductor devices having silicided electrodes

One embodiment of the invention relates to a method for fabricating a semiconductor device having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate. The method comprises forming a metal cluster layer from a first, non-siliciding metal, followed by the deposition of a metal layer consisting of a second, siliciding metal. A subsequent heat treatment is responsible for forming a metal silicide from the second metal, the atoms of the first metal being displaced in a direction substantially perpendicular to the surface of the substrate. According to one embodiment of the invention, the atoms of the first metal are displaced by the Kirkendall effect to beneath the metal silicide. If an MOST, for example, is being fabricated, this has advantages both at the location of the source and drain region and at the location of the gate electrode.

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Leuven, Belgium

Jacob Christopher Hooker