United Microelectronics Corp.

Jacob Chen

Yung-Chang Lin

Tung-Po Chen

Keh-Ching Huang

Wen-Jeng Lin

Tz-Guei Jung

Tri-Rung Yew

Shih-Wei Sun

Tong-Yu Chen

H J Wu

Chian-Gauh Shih

Cheng-Ju Hsieh

Jaris Yeh

A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the logic region. The MOS transistor comprises a gate, a source/drain region and a cap insulating layer on the gate. An etching stop layer is formed on the substrate to cover the MSO transistor and the STI structure. A dielectric layer is formed in the etching stop layer. The dielectric layer, the etching stop layer and the cap insulating layer are partially removed to form a first opening according to the pattern of a first mask layer. The first opening exposes the gate. According to the pattern of a second mask layer, the dielectric layer and the etching stop layer are partially removed to form openings, which expose the source/drain region, in the dielectric layer.

Method of forming borderless contact

A method of manufacturing wells comprises the step of providing a p-type substrate and then sequentially forming a p-well and n-well with low dosage in the p-type substrate. Thereafter, energy is used to dope n-type ions into the p-well. The triple well formed in the present invention has low dosage ions, hence the DRAM formed on the triple well in subsequent process can have a faster refresh time.

Method of fabricating well

In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain region. The insulating layer on a gate and a source/drain region in a logic region and a gate in a memory region. Salicide layers are formed on the three regions mentioned above. Formation of the salicide layers can lower resistance of the three regions, increase speed and can avoid forming a salicide layer on the source/drain region in the memory region. Thus, current leakage can be avoided. In addition, the step of forming a salicide layer is conducted after the annealing process of the source/drain region, so problems of thermal stability and inter-diffusion of impurities in the polysilicon layer can also be solved.

Method of forming salicide in embedded dynamic random access memory

The invention provides a manufacturing method of forming a bottom plate for a capacitor on a substrate, wherein the substrate comprises a MOS transistor having a gate and a pair of source/drain regions. A crown-liked conductive plate is formed over an insulation oxide layer and a contact plug. The crown-liked conductive plate penetrates the insulation layer and the stop layer, wherein the bottom of the crown-like conductive plate is electrically connected to the contact plug. The crown-like conductive plate, served as the bottom plate for a DRAM capacitor, is composed of tungsten silicide or a combination of a tungsten nitride layer and a tungsten layer.

Manufacturing method of a bottom plate

A method of fabricating a self-aligned contact. A substrate is defined as a memory region and a logic region. Metal oxide semiconductors and source/drain regions are respectively formed in the memory region and in the logic region. A defined dielectric layer is formed over the substrate. Contact holes are respectively formed in the memory region and in the logic region until the source/drain regions are exposed. Silicide layers are formed over the contact holes. Portions of the silicide layer extend to surface of the dielectric layer neighboring the contact holes. A defined inter-layer dielectric layer is formed over the substrate. Vias are respectively formed in the memory region and in the logic region. The vias are filled with conductive layers. The self-aligned contact is formed.

Method of fabricating self-aligned contact in embedded DRAM

A method for forming a dual polycide gate. A substrate that has an isolation structure is provided, a polysilicon layer (or an &agr;-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a dual gate having an N-type gate and a P-type gate. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a polycide gate, a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.

Method for forming polycide dual gate

A MOS gate manufacturing operation is capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate. The thin oxide layer is capable of protecting the barrier layer against acid corrosion without causing any noticeable increase in gate conductivity.

Manufacturing method capable of preventing corrosion and contamination of MOS gate

A manufacturing method is capable of preventing corrosion of a metal oxide semiconductor. The manufacturing method sequentially forms a polysilicon layer, a silicide layer and a top cap layer over a substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the silicide layer. Finally, the substrate is cleaned, and then of a source/drain region having a lightly doped drain structure is formed on each side of the gate.

Manufacturing method capable of preventing corrosion of metal oxide semiconductor

An improved formation method produces a metallic fuse capable of lowering the laser power needed for carrying out circuit repair. The method includes forming a metallic fuse when the penultimate metallic layer is formed. Since the metallic fuse is not too far away from the top surface, the power of the laser beam necessary for repairing the circuit can be moderate. Furthermore, the laser beam is more focused because it travels a shorter distance to reach the fuse, thereby avoiding unnecessary dispersion through intermediate material. Moreover, since the metallic fuse itself is not too thick, only a low-power laser beam is needed to melt the metallic fuse.

Method of forming metallic fuse demanding lower laser power for circuit repair

A method includes a self-aligned silicide (Salicide) technology in fabrication of an embedded dynamic random access memory (DRAM). On a silicon wafer, a first MOS transistor is formed in a logic device region, and second MOS transistor is formed in a memory device region. The improved method includes forming an insulating layer over the substrate at least covering the first (second) MOS transistor. A top portion of the insulating layer is removed to expose only a top portion of the first (second) gate structure. A portion of the insulating layer covering the first MOS transistor is removed to expose the first MOS transistor. Using the remaining insulating layer on the second MOS transistor as a mask, the Salicide fabrication process is performed to form a self-aligned silicide layer on the first interchangeable source/drain region, and the exposed top surface of the first (second) polysilicon gate structure.

Method for fabricating an embedded dynamic random access memory using

An integrated circuit device having both an array of logic circuits and an array of embedded DRAM circuits is provided using a process that avoids some of the most significant processing challenges for embedded DRAM integration. Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device in an initial phase of the process. The gate electrodes and source/drain regions of the logic FETs are subjected to a salicide process at this initial phase and a thick planarized oxide layer is provided over both the embedded DRAM regions and the logic circuit regions. Capacitors and logic interconnects are next formed using common etching, titanium nitride deposition and tungsten deposition steps. Contact vias are formed to expose each of the source drain regions of the DRAM transfer FETs and to expose select conductors within the logic circuits. A titanium nitride layer is deposited over the device and within the various contact vias through the planarized oxide layer. A capacitor dielectric layer is provided over the device and then the capacitor dielectric layer is selectively removed from at least the contact vias that become bit line contacts and logic interconnects. A layer of tungsten is deposited and patterned to provide upper capacitor electrodes and to complete the bit line contacts and logic interconnects. This first level tungsten layer also can provide bit line wiring. The 1/2 V.sub.cc potential for the upper capacitor electrodes can be provided to the circuit using a level of interconnect wiring also used by the logic circuits.

Process and structure for embedded DRAM

A power source design for embedded memory uses independent power sources such that a first power source group is linked to the DRAM, a second power source group is linked to the logic unit and a third power source group is linked to the testing mode circuit with input/output ports during the silicon chip stage. In the packaging stage the first power source group, the second power source group and the third power source group are joined together. The design is able to prevent testing errors or instability due to direct current from floating nodes in the silicon chip testing stage, and prevent a potential latch-up problem in the packaging stage.

Growing community of inventors

Hsinchu, Taiwan

Jacob Chen