Koninklijke Philips Corporation N.V.

Nxp B.v.

Jacky Talayssat

Anne Lafage

Lien Nguyen-Phuc

Sake Buwalda

A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip.

JTAG test architecture for multi-chip pack

The present invention relates to a memory circuit (MEM) able to receive a first data block comprising a number of components and coming from an external memory (EXT) for them to be written (W) in an internal memory. The memory circuit is also able to supply (R) to an output device (FIL) a second data block comprising a component of said data. The memory circuit comprises data banks able to receive data words, and address controllers associated to the data banks and able to organize a reading or writing access of the data in the internal memory of the memory circuit, while minimizing the number of data banks used. Thus it is possible to rapidly read or write in the memory circuit at relatively low cost.

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Chateauneuf, France

Jacky Talayssat