Texas Instruments Corporation

Jackson Leung

Brian L Brown

Ronald J Syzdek

Pow Cheah Chang

A semiconductor memory device ( ) having a parallel test circuit is disclosed. A test data path ( ) receives parallel I/O line (I/O -I/O ) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit ( ). The gate control circuit ( ) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver ( ) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit ( ), the open drain output driver ( ) drives a data output (DQ) to a first, second or intermediate logic level.

Current controlled multi-state parallel test for semiconductor device

A semiconductor memory device ( ) having a parallel test circuit is disclosed. A test data path receives parallel I/O line (I/O -I/O ) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a two-bit register ( ) and output in a sequential fashion to an open drain output driver ( ). In this manner, test result data values are provided by driving an output (DQ) in a rapid sequential fashion, rather than placing the output at one of three states (such as logic high state, a logic low state, or a high impedance state).

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Jackson Leung