Skyworks Solutions, Inc.

Wionics Research

Realtek Semiconductor Inc.

Orion Microelectronics Corporation

Jackie K Cheng

Kuangyu Li

Alyosha C Molnar

Zaw Soe

Kuang-Yu Yen

Rahul Magoon

Evan S McCarthy

Jeffrey M Zachan

Tony Yang

Tom Baker

Liang-Hui Lee

Sining Zhou

Madhukar Reddy

Fei-Ran Yang

Shoufang Chen

Thomas Francis Baker

Song-Nien Tang

The present invention provides a TV receiver and an analog TV signal processing method. The TV receiver includes a tuner, an analog-to-digital converter, and a digital filter module. The tuner is utilized to receive an RF signal and generate a first signal; the analog-to-digital converter is coupled to the tuner for converting the first signal to a digital signal, and the digital filter module is coupled to the analog-to-digital converter for filtering the digital signal in order to filter an analog TV signal contained in the RF signal in digital domain.

TV receiver and analog TV signal processing method

Multistage RF transmitter and receiver circuits may use independently variable RF and IF local oscillators, allowing the RF and IF local oscillator frequencies for a given RF channel to be selected to have a large common factor with respect to the reference oscillator used by the local oscillator circuits, thus allowing the use of small divisor numbers in the local oscillator circuits and reducing phase noise. Independent high-side and low-side RF local oscillators may be provided and selectively used depending on the RF channel to be transmitted or received.

Multiple band RF transmitters and receivers having independently variable RF and IF local oscillators and independent high-side and low-side RF local oscillators

Systems and methods for canceling static and dynamic DC offsets by combining a digital DC offset correction scheme with an analog DC offset correction scheme. A feedback-based digital DC offset correction scheme provides different adjustment levels for a plurality of discrete gain states and the analog DC offset correction scheme operates in different cancellation modes dependent on a frame structure. A digital DC offset correction scheme collects DC offset control information and provides adjustment levels. In addition, a negative-feedback based switchable high pass filter has a plurality modes of operation, where one mode of operation includes an all-pass filter.

Hybrid DC offset cancellation scheme for wireless receiver

A feedback system has a settling time that is independent of the forward gain of the amplifier stage, and a feedback path that is responsive to the magnitude of DC offset in the output signal. Settling time may be made independent of the forward gain of the amplifier stage by providing a constant loop gain in the amplifier stage through active gain control of both the forward and linear feedback amplifier elements. The feedback path may be made responsive to the magnitude of DC offset in the output signal by providing a non-linear transconductance in the feedback path that varies the high pass corner and hence the DC offset reduction time of the amplifier stage in response the magnitude of DC offset in the output signal.

Apparatus and method for DC offset reduction

An output stage circuit for a current mode device provides open loop reduction or cancellation of DC offset in differential output signals. Differential input signals are received and sourcing current mirrors provide mirrors of the differential input signals to output nodes. Sinking current mirrors also provide mirrors of opposite polarity of the differential input signals to the output nodes corresponding to the opposing sourcing current mirrors. The summing of the mirror currents at the output nodes substantially reduces or eliminates the DC offset components present in the input signals.

Current mode output stage circuit with open loop DC offset reduction

Embodiments of the invention provide techniques for calibrating voltage-controlled oscillators (VCOs). Multiple VCOs may be disposed on a chip with the VCOs having different frequency ranges. The VCOs may be selected and tested to determine a desired VCO to use to tune to a selected channel frequency. Each of the VCOs has multiple possible varactor configurations. The varactor configurations of the desired VCO determined to be used to tune to the selected channel frequency can be selected and tested to determine a desired varactor configuration for the desired VCO. The desired VCO with the desired varactor configuration will preferably be able to produce a full range of desired frequencies corresponding to all channel frequencies desired.

On-chip VCO calibration

Techniques are provided for compensating for variations in capacitance of capacitors used in resonant circuits, particularly varactors used in voltage-controlled oscillators. Indications of actual varactor capacitances are used to determine which of several inductances to use in the resonant circuit with the varactor. The inductances may be composed of a bondwire inductance, and may also be composed of one or more coil inductors. Based on the determined capacitance indication, a bondwire is connected from a common bondpad to a selected bondpad to complete the resonant tank circuit such that an LC product of the tank circuit is within a desired or acceptable LC product range.

VCO resonance tuning

A programmable capacitive network for use in a tunable resonant circuit is set forth that may be used in a number of different applications, but is particularly useful in the tuning of a voltage controlled oscillator formed on a substrate, such as a semiconductor substrate or the like. The programmable capacitive network includes a plurality of capacitive elements. An interconnected network of voltage gate elements and fuse elements are interconnected with the capacitive elements to selectively connect one or more of the plurality of capacitive elements in the resonant circuit in response to at least one program control signal. In accordance with one embodiment, the voltage gate elements are diodes.

Tunable resonant circuit and voltage controlled oscillator using same

A tuning circuit for use in tuning multiple voltage-controlled oscillators (VCOs) of a phase-locked loop (PLL) is provided. A search algorithm is used to determine which VCO to use for a given frequency to be synthesized by the PLL. The tuning circuit provides a binary representation, associated with the frequency to synthesize, to the PLL. The PLL responds to this representation by attempting to synthesize the associated frequency. New binary representations are provided until an indication of a threshold frequency between multiple VCOs is determined. A record of the threshold frequency is stored. The binary representation of a frequency to be synthesized and the stored record of the threshold frequency are used to provide an indication of which VCO of the PLL to use to synthesize the desired frequency.

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Irvine, CA, United States of America

Jackie K Cheng