Advanced Micro Devices Corporation

Virtual Silicon Technology, Inc.

Jackie Chu

Yikai Liang

Olivier A Saint-Luc

Methods and apparatuses are provided for duty cycle correction of high-speed clock circuits. The apparatus includes a duty cycle interpolator receiving a clock source for providing a duty cycle corrected clock signal. The duty cycle corrected clock signal is filtered and compared to a reference signal, the result of which is clocked into a shift register. The shift register provides complementary N-bit duty cycle correction signals to the duty cycle interpolator for adjusting the duty cycle of the clock signal to provide the duty cycle corrected clock signal. The method includes filtering a duty cycle corrected clock signal to provide a filtered signal and comparing the filtered signal to a reference signal, the result of is clocked into a shift register. The shift register provides complementary N-bit duty cycle correction signals to a duty cycle interpolator for adjusting the duty cycle of a clock signal.

Method and apparatus for correcting the duty cycle of a high speed clock

An input stage circuit for an LVDS circuit. The input stage has a folded cascode that receives input signals. The folded cascode has a first input circuit and a second input circuit. The first input circuit receives a first input signal from a connected circuit and the second input circuit receives a second signal from the connected circuit. A first current mirror receives signals from the first input circuit of said folded cascode. A second current mirror receives signals from the second input circuit. The first current mirror and the second current mirror are connected to a common output to merge signals from the first and second input circuits. A diode adjusts a voltage level of the signals to an output voltage.

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Fremont, CA, United States of America

Jackie Chu