Taiwan Semiconductor Manufacturing Comp. Ltd.

Jack Yeh

Chia-Ta Hsieh

Di-Son Kuo

Hung-Cheng Sung

Yai-Fen Lin

Wen-Ting Chu

Chrong-Jung Lin

Chrong Jung Lin

Chung-Li Chang

Te-Hsun Hsu

Chuan-Li Chang

Derek Lin

Sheng-Wei Tsaur

Sheng-Wei Tsao

Yung-Tao Lin

A non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source/drain region of the transistor is connected to the first doped region of the first capacitor.

Logic compatible storage device

A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

Method to increase coupling ratio of source to floating gate in split-gate flash

A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.

Method of making the selection gate in a split-gate flash EEPROM cell and its structure

Method of making the selection gate in a split-gate flash eeprom cell and its structure

A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the miniaturized circuits of the ultra scale integrated technology. Furthermore, it is well known that GBB encroaches under the gate edge in a split-gate flash and degrades the programmability of submicron memory cells. The sharp poly tip of the invention is provided by forming a tapered floating gate through a high pressure etch such that the tip of the upper edge of the floating gate under the poly oxide is sharper and more robust, and, therefore, less susceptible to damage during the manufacture of the cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

Method to fabricate poly tip in split gate flash

A method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is described. Active areas are separated by isolation regions in a substrate. A gate oxide layer is grown on the active areas. A conducting layer is deposited overlying the gate oxide layer and patterned to form gate electrodes in the active areas and to form conductive strips overlapping both the active areas and the isolation areas at an isolation's edge on a drain side of the active areas wherein the conductive strips reduce the electric field at the isolation's edge in the fabrication of an integrated circuit device.

Adding a poly-strip on isolation's edge to improve endurance of high voltage NMOS on EEPROM

A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers subsequent to the forming of the inter-poly oxide is avoided. Consequently, the variation in the thickness of the inter-poly oxide due to the unpredictable damage to the underlying spacers is also avoided by reversing the order in which the spacers and the inter-poly oxide are formed, including the forming of the pad oxide first. As a result, variation in the erase speed of the inter-gate flash memory cell is prevented, both for cells fabricated on the same wafer as well as on different wafers on same or different production lines.

Split gate flash memory device having nitride spacer to prevent inter-poly oxide damage

Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transistor (FET) device. Similarly, there is also formed within the split gate field effect transistor a floating gate electrode within the trench and covering within the trench a lower sub-portion of the channel region. Finally, the floating gate electrode in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel. The split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.

Vertical split gate field effect transistor (FET) device

A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory cell. In a first embodiment, the close self-alignment is made possible through a new use of an anti-reflective coating (ARC) in the various process steps of the making of the cell. In the second embodiment, a low-viscosity material is used in such a manner so as to enable self-alignment of the floating gate to the STI in a simple way.

Method of forming a floating gate self-aligned to STI on EEPROM

A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed over a second polysilicon layer forming the control gate. However, the second polysilicon layer is also formed over the source region and overlying the other otherwise exposed portion of the floating gate such that this additional poly line now shares the voltage between the source and the floating gate, thereby reducing punch-through and junction breakdown voltages. In addition, the presence of another poly wall along the floating gate increases the coupling ratio between the source and the floating gate, which in turn improves program speed of the split-gate flash memory cell.

A method is provided to improve the control of bird's beak profile of poly in a split gate flash memory cell. The control of the bird's beak profile is achieved in a first embodiment where the polycrystalline layer of the floating gate is annealed at a high temperature. The annealing promotes small grain size and hence smoother surface in the polysilicon, which in turn promotes sharper poly tip. The smoother poly surface also results in thinner inter-poly between the floating gate and the control gate, which together with the sharp poly tip, enhances the erase speed of the split-gate flash memory cell. In a second embodiment, the performance is further enhanced by providing an amorphous silicon for the floating gate, because the amorphous nature of the silicon yields a very smooth surface. This smooth surface is transferred to the recrystallized state of the silicon layer through annealing. Thus, a good control for the bird's beak is achieved. A sharp and short poly tip then results from a well controlled and well-defined bird's beak. Hence, an enhanced split-gate flash memory cell follows.

Method to improve the control of bird's beak profile of poly in split gate flash

A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion. A polysilicon layer is formed over the interpoly oxide layer. The structure is patterned to form a floating gate/word line device.

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Hsin-Chu, Taiwan

Jack Yeh