Microchip Technology Inc.

Jack Wynne

Ihab Jaser

Nima Nikuie

Xin Guo

Donia Sebastian

Kwok Kong

An apparatus and method for scheduling memory requests including receiving a plurality of requests having a type and associating each request of the received plurality of requests with a corresponding target, which is associated with one channel of a plurality of channels. The method assigning a priority to each request, assigning a utilization cost to each request based on the request's target and request type, and queueing each request of the plurality of requests for scheduling. The method selecting a first request of the received plurality of requests to be scheduled based on its priority, scheduling the first request for processing at a time when the first request utilization cost is less than or equal to a current value of a dynamic utilization counter, and debiting the dynamic utilization counter by the first request utilization cost.

System and method for centralized management of workload and parallel service of prioritized requests

An apparatus and method including a command input to receive a command with a macro identifier from a channel processor, a macro memory storing a plurality of flash control commands, each comprising a duration and a plurality of target control values to control a flash target; and a second finite state machine comprising a plurality of control outputs each corresponding control inputs on the flash target, wherein in response to a received command, the first finite state machine locates in the macro memory a sequence of flash control commands associated with the macro identifier and sequentially outputs the flash control commands to the second finite state machine; and wherein the second finite state machine drives each of the plurality of control outputs based on corresponding values in the first flash control command for the duration specified in the current flash control command.

Protocol agnostic control of NAND flash

An apparatus and method for dispatching flash commands. The apparatus includes a plurality of queues, wherein each queue comprises an input to receive a flash command, an output to send a flash command, and an empty signal output to signal when the queue is empty, wherein each queue is assigned a unique, ordered priority. The apparatus includes a selector comprising a plurality of flash command inputs, a flash command output to a flash target, and a selection input, wherein each flash command input is coupled to a corresponding queue output. The apparatus includes an arbiter comprising inputs receiving each queue empty signal and receiving a lock bit from the flash command output of the selector and comprising a selection output coupled to the selection input of the selector. The flash command comprises a lock bit and a plurality of control bits to output to control inputs on a flash target.

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Los Altos, CA, United States of America

Jack Wynne