Motorola Corporation

Jack Wu

Christopher Neal Hinds

Daniel T Marquette

A zero detection method (FIG. 5) and a zero detection apparatus (FIGS. 2-4) involves determining if the sum of at least two operands and a carry-in bit will produce a zero result. The zero detection is performed in parallel to another system calculation, such as an addition or subtraction of the two operands. The zero detection logic has a hierarchical structure (see FIG. 4) which is used to reduce logic and quicken the zero detect process of FIG. 5. Zero detection may occur for more than one group of bits within the two operands. The zero detection is used, in a preferred form, primarily in floating point operations such as floating point additions.

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Austin, TX, United States of America

Jack Wu