Microchip Technology Inc.

Jack Wong

Sonu Daryanani

Mel Hymas

Bomy A Chen

Kent D Hewitt

Jeffrey A Shields

Sajid Kabeer

Santosh Murali

Brad Kopp

Daniel Alvarez

Neil Deustcher

Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

Method of forming a polysilicon sidewall oxide region in a memory cell

An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

EEPROM memory cell with low voltage read path and high voltage erase/write path

A method for integrating non-volatile memory with high-voltage and low-voltage logic in a salicide process is disclosed. The method includes forming a source region and a drain region associated with a gate region for each of a low-voltage (LV) device, a high-voltage (HV) device and a non-volatile memory (NVM) device. The HV, LV and NVM devices are electrically isolated by a field oxide region located adjacent to the respective source and drain regions. The field oxide regions are implanted with an isolation implant, such that the field implant is spaced a predetermined distance away from the HV and NVM source and drain regions. A blanking layer is deposited on the field oxide regions and a portion of the source and drain regions associated with the HV and NVM devices. Doped metal salicide regions are formed on the LV source and drain regions, all gate regions, and the exposed portions of the HV and NVM source and drain regions not covered by the blanking layer.

Method for integrating non-volatile memory with high-voltage and low-voltage logic in a salicide process

A merged two-transistor memory cell of an EEPROM, and method of fabricating the cell, are provided. The memory cell includes a substrate and gate oxide layer formed on the substrate. It also includes a memory transistor having a floating gate and a control gate, and a select transistor having a gate that is shared with the memory transistor. The memory cell is configured so that the shared gate serves both as the control gate of the memory transistor and the wordline of the select transistor. The memory cell further includes a dielectric layer that is disposed between the floating gate and the shared gate. The dielectric layer is defined by an ONO film and a stacked oxide layer. In fabricating the memory cell, the ONO stack film is formed adjacent to the top surface of the floating gate and the stacked oxide layer is formed adjacent to the side surface of the floating gate.

Dielectric layer of a memory cell having a stacked oxide sidewall and

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Jack Wong