Lattice Semiconductor Corporation

Advanced Micro Devices Corporation

Vantis Corporation

Globalfoundries Inc.

Marvell International Limited

Globalfoundries Singapore Pte. Ltd.

Jack Tim Wong

Om P Agrawal

Fabiano Fontana

Bradley A Sharpe-Geisler

Bai Yen Nguyen

Howard H Tang

Herman M Chang

Wuyang Hao

Henry Law

Jeffrey S Byrne

Chunsung Chiang

Clark Wilkinson

Kory Gong

Martha Chan

Susan Nguyen

Eng Huat Toh

Kangho Lee

Ju Shen

Elgin Kiok Boone Quek

Giap H Tran

Yu Huang

Cyrus Y Tsui

Chan-Chi Jason Cheng

Benny Ma

Lejan Pu

Sam Tsai

Yentsai Huang

The present disclosure generally relates to semiconductor structures and, more particularly, to a single path memory sense amplifier circuit and methods of manufacture. The circuit includes a sense amplifier circuit comprising a plurality of self-aligned transistors in a single sensing path; and a memory array connected to the sense amplifier circuit by the single sensing path.

Single path memory sense amplifier circuit

The present disclosure relates to a structure which includes a merged write driver circuit with a first device next to a first memory array and a second device next to a second memory array, and the merged write driver circuit being configured to share a write driver line between the first device and the second device.

Merged write driver based on local source line MRAM architecture

A spin transfer torque magnetic random access memory (STT-MRAM) device and a method to perform operations of an embedded eFlash device are disclosed. The STT-MRAM device is configured to include an array of STT-MRAM bitcells. The array includes a plurality of bitlines (BLs) and a plurality of word lines (WLs), where the bitlines form columns and the wordlines form rows of STT-MRAM bitcells. Each STT-MRAM bitcell includes a magnetic tunnel junction (MTJ) element coupled in series to an access transistor having a gate terminal and source and drain terminals. The array includes a plurality of source lines (SLs) coupled to the source terminals of the access transistors. A SL of the plurality of SLs is coupled to source terminals of access transistors of two or more adjacent columns of the STT-MRAM cells. The shared SL is parallel to the plurality of BLs. The operations of such a STT-MRAM bitcell are configured to include: an initialization operation, a program operation, and a sector erase operation.

STT-MRAM bitcell for embedded flash applications

In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks adapted to precondition registers within the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.

Transparent field reconfiguration for programmable logic devices

Systems and methods are directed to verification of configuration data stored in memory cells. For example, in one embodiment, an integrated circuit such as a programmable logic device includes a plurality of non-volatile memory cells and a plurality of volatile memory cells adapted to receive and store data provided from the plurality of non-volatile memory cells. A comparator is adapted to compare stored data from the plurality of volatile memory cells with the data values of the plurality of non-volatile memory cells. Control circuitry is responsive to the comparator to control whether configuration data from the plurality of non-volatile memory cells is loaded to the plurality of volatile memory cells.

Data transfer verification systems and methods

In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks having boundary scan cells that are adapted to precondition registers within a logic area of the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.

Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and includes multiple data ports for programming the flash memory and/or the SRAM.

Upgradeable and reconfigurable programmable logic device

Systems and methods are directed to verification of configuration data stored in memory cells. For example, in one embodiment, an integrated circuit includes a first plurality of memory cells including a first set of test memory cells. A second plurality of memory cells is adapted to receive and store data provided from the first plurality of memory cells. The second plurality of memory cells include a second set of test memory cells corresponding to the first set of test memory cells. A comparator is adapted to compare stored data from the second set of test memory cells with the data values of the first set of test memory cells. Control circuitry is responsive to the comparator to control whether additional data from the first plurality of memory cells is loaded to the second plurality of memory cells.

A field programmable gate array (FPGA) has plural columns of run-time memory provided in each of one or more partitions. Each column of run-time memory has a plurality of configurable memory blocks (CMB's). Each CMB is programmably configurable at least into a shallow-and-widest mode where data words have a maximum bit width and into a deep-and-narrowest mode where data words have a minimum bit width. Each CMB spans plural interconnect buses and the bits of its widest data words are distributed among the spanned interconnect buses. When a deep-and-narrow mode is invoked, CMB's of alternate columns operate in complementary fashion so that bits of narrowed words from one CMB move through a first subset of the interconnect buses while bits of narrowed words from a second CMB, in an alternate column, move through a second subset of the interconnect buses, where the second subset is mutually exclusive of the first subset of the interconnect buses. On the other hand, when the shallow-and-widest mode is invoked, the bits of the wide words of CMB's in alternate columns shared interconnect buses on an overlapping basis. In one embodiment, the shared interconnect buses are tri-statable. Programmable joiners are provided for joining or disjoining the tri-statable interconnect buses of adjacent partitions.

Field programmable gate array having embedded memory with configurable depth and width

An integrated circuit includes non-volatile and volatile memory, with the volatile memory controlling the integrated circuit's functionality. Various techniques are disclosed for programming the different types of memory through one or more data ports to provide in-system programmability and dynamic reconfigurability. External configuration devices are not required if the data from the non-volatile memory is transferred directly to the volatile memory.

Non-volatile and reconfigurable programmable logic devices

A logic array device has an array of plural interconnect resources including plural lines and plural switchbox areas, with an array of plural Variable Grain Blocks (VGB's) interspersed within the array of plural interconnect resources. The array of plural interconnect resources does not regularly include lines of single-length or shorter, and the array of plural interconnect resources does not regularly include switchbox areas that are spaced apart from one another by distances of a single-length or shorter. The single-length corresponds to a traverse of a continuous distance covering approximately one VGB.

Efficient interconnect network for use in FPGA device having variable

A tileable structure is provided for logic array devices. The tileable structure has a mirror-symmetrical arrangement of sets of logic blocks, common control sections for the logic block sets, surrounding interconnect lines, and switching areas at intersections of the interconnect lines.

Tileable and compact layout for super variable grain blocks within FPGA

A cell array circuit for a programmable logic device is provided with split read and write lines in the memory cell. The circuit eliminates the need for pass gates in the speed path. The circuit includes steering logic, a row line driver circuit and a row decoder circuit to facilitate the different modes of operation of the cell array circuit.

Growing community of inventors

Fremont, CA, United States of America

Jack Tim Wong