Microsoft Technology Licensing, LLC

Meta Platforms Technologies, LLC

Jack Thomas Lavier

Daniel Max Firestone

Andrew Richard Putnam

Gregory Mayo Daly

Derek Chiou

Robert Glenn Rundell

Shlomo Alkalay

Julia Jacinta Busono

Systems and readout methods for foveated sensing may include a pixel array, readout circuitry, and processing logic. The pixel array may have a number of pixels. The readout circuitry may be configured to read image data from the pixel array for each of the plurality of pixels. The processing logic may be configured to identify a number of regions of interest (ROIs) within the pixel array. The processing logic may be configured to associate the image data for the pixels with one or more ROIs. The processing logic may be configured to arrange the image data into data frames. The data frames may include the image data ordered by ROI. Image data for inactive pixels may be removed from the image data and data frames prior to transmission. The processing logic may be configured to transmit the data frames in an order that is based on the ROIs.

Readout methods for foveated sensing

A method includes accessing a scene graph defining a spatial relationship of a plurality of first bounding boxes associated with a plurality of virtual objects in a field of view of a user of an artificial reality (AR) device; accessing a second bounding box associated with a first bounding box of the plurality of first bounding boxes; determining, based on the second bounding box, a subregion within a sensing region of a depth sensor; obtaining first depth data within the subregion; generating, based on the first depth data, a three-dimensional model for one or more real objects; determining a visibility of a first virtual object in the AR environment associated with the first bounding box based on the three-dimensional model for the one or more real objects; and generating an output image of an AR environment based on the determined visibility of the first virtual object.

Systems and methods for generating dynamic occlusion information

A physical server with an offload card including a SoC (system-on-chip) and a FPGA (field programmable gate array) is disclosed. According to one set of embodiments, the SoC can be configured to offload one or more hypervisor functions from a CPU complex of the server that are suited for execution in software, and the FPGA can be configured to offload one or more hypervisor functions from the CPU complex that are suited for execution in hardware.

Server offload card with SoC and FPGA

Examples are disclosed that relate to oscillator circuits. One example provides a circuit comprising an amplifier, a resonator in parallel with the amplifier, and a shunt path including one or more circuit elements, the shunt path coupled to a first node downstream of an output of the amplifier and to a second node, the shunt path configured to shunt current received at the first node away from an input of the resonator and toward the second node, the second node having, at steady state, a relatively lower voltage than an input voltage of the resonator.

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Sammamish, WA, United States of America

Jack Thomas Lavier