Intel Corporation

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Sony Group Corporation

Google Inc.

Tahoe Research, Ltd.

Sony Corporation

Intel Corporatuon

Intel Corporatiion

Sk Hynix Nand Product Solutions Corp.

Jack T Kavalieros

Gilbert W Dewey

Matthew V Metz

Robert S Chau

Willy Rachmady

Van H Le

Tahir Ghani

Ravi Pillarisetty

Suman Datta

Benjamin Chu-Kung

Marko Radosavljevic

Justin K Brask

Mark L Doczy

Brian S Doyle

Anand S Murthy

Niloy Mukherjee

Abhishek A Sharma

Seung Hoon Sung

Uday Shah

Cheng-Ying Huang

Glenn A Glass

Sean T Ma

Harold W Kennel

Been-Yih Jin

Chandra S Mohapatra

Shriram Shivaraman

Mantu K Hudait

Han Wui Then

Ashish Agrawal

Niti Goel

Nazila Haratipour

Prashant Majhi

Rafael Rios

Amlan Majumdar

Stephen M Cea

Titash Rakshit

Ian A Young

Chris E Barns

Uygar E Avci

Aaron D Lilak

Sansaptak W Dasgupta

Sanaz Kabehie Gardner

Yih Wang

Roza Kotlyar

Bernhard Sell

Karthik Jambunathan

Pei-Hua Wang

Patrick R Morrow

Seiyon Kim

Wilman Tsai

Chieh-Jen Ku

Scott A Hareland

Anh Phan

Travis W LaJoie

Kelin J Kuhn

Chia-Ching Lin

Ehren Mannebach

Martin D Giles

Cory C Bomberger

Ashish Verma Penumatcha

Hui Jae Yoo

Fatih Hamzaoglu

Kimin Jun

Annalisa Cappellani

Cory E Weber

Mark Y Liu

Miriam Ruth Reshotko

Rishabh Mehandru

Peter G Tolchinsky

Sasikanth Manipatruni

Ram K Krishnamurthy

Charles C Kuo

Raghavan Kumar

Gregory Kengho Chen

James M Blackwell

Reza Arghavani

Phil Knag

Huseyin Ekin Sumbul

Daniel Bourne Aubertine

Amrita Mathuriya

Kevin Lai Lin

Elijah V Karpov

Boyan Boyanov

Christopher J Jezewski

Nick Lindert

Mark T Bohr

Tanay Gosavi

Valluri Ramana Rao

Nicole K Thomas

Scott Bruce Clendenning

Brian E Roberds

Dinesh Somasekhar

Valery M Dubin

Biswajeet Guha

Michael L Hattendorf

Wilfred Gomes

Richard E Schenker

David L Kencke

Kunjal ShyamKumar Parikh

Sean W King

A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Nanowire transistor fabrication with hardmask layers

Gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a sub-fin structure, wherein individual ones of the vertical arrangement of nanowires include silicon and germanium, and wherein the sub-fin structure has a relatively higher germanium concentration at a top of the sub-fin structure than at a bottom of the sub-fin structure.

Gate-all-around integrated circuit structures having germanium-diffused nanoribbon channel structures

Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.

Transistor gate trench engineering to decrease capacitance and resistance

Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

Capacitor connections in dielectric layers

A gate-all-around transistor device includes a body including a semiconductor material, and a gate structure at least in part wrapped around the body. The gate structure includes a gate electrode and a gate dielectric between the body and the gate electrode. The body is between a source region and a drain region. A first spacer is between the source region and the gate electrode, and a second spacer is between the drain region and the gate electrode. In an example, the first and second spacers include germanium and oxygen. The body can be, for instance, a nanoribbon, nanosheet, or nanowire.

Formation of gate spacers for strained PMOS gate-all-around transistor structures

FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

Field effect transistors with a gated oxide semiconductor source/drain spacer

Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures

Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. An n-channel device and a p-channel device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where one device is located vertically above the other device. According to some embodiments, the n-channel device and the p-channel device conductively share the same gate, and a width of the gate structure around one device is greater than the width of the gate structure around the other device. According to some other embodiments, the n-channel device and the p-channel device each have a separate gate structure that is isolated from the other using a dielectric layer between them. A gate contact is adjacent to the upper device and contacts the gate structure of the other lower device.

Asymmetric gate structures and contacts for stacked transistors

A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes HfZO, where 0.33<x<0.5. The first transistor further includes a first gate electrode on the first gate dielectric layer and a first source region and a first drain region on opposite sides of the first gate electrode. The CMOS transistor further includes a second transistor adjacent to the first transistor. The second transistor includes a second gate dielectric layer above a second channel, where the second gate dielectric layer includes HfZO, where 0.5<x<0.99, a second gate electrode on the second gate dielectric layer and a second source region and a second drain region on opposite sides of the second gate electrode.

Gate dielectrics for complementary metal oxide semiconductors transistors and methods of fabrication

A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Transistor with isolation below source and drain

An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

Self-aligned interconnect structures and methods of fabrication

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

Integrated circuit structures having germanium-based channels

Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

Forksheet transistors with dielectric or conductive spine

Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Two transistor memory cell using stacked thin-film transistors

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

Forming an oxide volume within a fin

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Portland, OR, United States of America

Jack T Kavalieros