Tektronix, Inc.

Jack Sachitano

Tadanori Yamaguchi

Hee Kyung Park

Paul K Boyer

Gregory C Eiden

Shuichi Sato

A mixed bipolar-CMOS self-aligned process and integrated circuit provide a high performance NPN bipolar transistor in parallel to fabrication of a PMOSFET and an NMOSFET. Gate and base contacts are formed in a first polysilicon layer. The base contacts are implanted with P+ ion concentrations for diffusing base contact regions of the substrate in a later drive-in step. Source and drain contacts and emitter contacts are formed in a second polysilicon layer. The source and drain contacts are formed as a unit and then separated into discrete contacts by a spin-on polymer planarization and etch-back procedure. Lightly-doped lateral margins of the source, drain and base regions are ion-implanted in an initial low concentration (e.g. about 10.sup.13 atoms/cm.sup.2). The gate and base contact structures serve as a mask to self-align the implants. Then, the gate and base structures are enclosed in an oxide box having sidewalls. The second polysilicon layer, next deposited, is laterally spaced by the sidewalls from the first layer. The second layer is selectively implanted with dopant ions of appropriate type for each device: N-type for the NMOSFET and P-type for the PMOSFET and the base of an NPN bipolar transistor. A drive-in step diffuses the implanted ions into the substrate. A shallow P+ intrinsic base is formed, which is spaced from the P+ base contact diffusions by a lightly-doped margin. Then, the emitter contact polysilicon is implanted N+ and a drive-in step forms a shallow emitter within the P+ base. The FET device likewise have graduated doping profiles in their source and drain diffusions.

High speed double polycide bipolar/CMOS integrated circuit process

An intermediate structure in the fabrication of a metal-oxide semiconductor field-effect transistor is made from a substrate of p+ silicon having an elongate insulated gate structure on its main face. First and second areas of the main face are exposed along first and second opposite sides respectively of the gate structure. Donor impurity atoms are introduced into the substrate by way of at least the first area of the main face, to achieve a predetermined concentration of electrons in a region of the substrate that is subjacent the first area of the main face. The gate structure is opague to the impurity atoms. A sidewall of silicon dioxide is formed along the first side of the gate structure, whereby a strip of the first area of the main face is covered by the sidewall and other parts of the first area remain exposed adjacent the sidewall. Donor impurity atoms to which the gate structure and the sidewall are opaque are introduced into the substrate by way of the portion of the first area that is exposed adjacent the sidewall. A layer of polysilicon is disposite over the portion of the first area of the main face that is exposed adjacent the sidewall. This layer extends up the sidewall and over the gate structure. A layer of a polymer material is formed over the layer of polysilicon to a substantially uniform height over the main face. The height of the free surface of the layer of polymer material is at least as great as the maximum height of the layer of polysilicon over the gate structure. The polysilicon at a height that is at least as great as that of the gate structure is then removed.

Method of fabricating aLDD field-effect transistor

An improved, ultra high speed (2GHz) CMOS inverter structure comprising a double-diffused, planar p-channel transistor and a nonplanar n-channel transistor formed within adjacent surface fields on the same substrate. The n-channel device includes a source region formed in an elevated, plateau region on the substrate, and a narrow, implanted channel-forming layer that extends through the plateau beneath the source region and terminates at a slope joining the plateau to surrounding lower elevation portions of the substrate. A drain region is formed adjacent the foot of the slope, spaced from the channel to provide a drift region between them.

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Portland, OR, United States of America

Jack Sachitano